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111 条记录 (耗时 0.031 秒)

    Inverse-vector method for smoothing dips and azimuths
    41.
    发明授权
    Inverse-vector method for smoothing dips and azimuths 有权
    用于平滑凹陷和方位角的逆矢量方法

    公开(公告)号：US07454292B2

    公开(公告)日：2008-11-18

    申请号：US11787246

    申请日：2007-04-13

    申请人： Yuchun Eugene Wang ,  Yi Luo ,  Mohammed N. Alfaraj

    发明人： Yuchun Eugene Wang ,  Yi Luo ,  Mohammed N. Alfaraj

    IPC分类号： G06F17/50

    CPC分类号： G01V1/28

    摘要： A system and method using inverse-vector processing to iterate through a loop of three steps: set a guide direction, invert opposite vectors, and average vectors to update the guide direction, for smoothing seismic amplitude data. The inverse-vector method can overcome instabilities where the traditional structure-tensor approach fails. The inverse-vector smoothing is simple to implement and more computational efficient. The resultant dips and azimuths are spatially consistent and thus more interpretable and suitable for calculation of curvature and other dip based attributes.

    摘要翻译： 一种使用逆向量处理来迭代三个步骤的循环的系统和方法：设置引导方向，反向向量反转和平均向量以更新引导方向，以平滑地震幅度数据。 逆向量法可以克服传统结构张量方法失效的不稳定性。 逆矢量平滑实现简单，计算效率更高。 所得到的倾斜和方位角在空间上是一致的，因此更可解释并且适合于计算曲率和其他基于倾斜的属性。

    Method and apparatus for an anti-theft system against radio relay attack in passive keyless entry/start systems
    42.
    发明申请
    Method and apparatus for an anti-theft system against radio relay attack in passive keyless entry/start systems 有权
    无源无钥匙进入/启动系统中防盗系统的无线电中继攻击的方法和装置

    公开(公告)号：US20080143500A1

    公开(公告)日：2008-06-19

    申请号：US11639915

    申请日：2006-12-15

    申请人： Riad Ghabra ,  Yi Luo ,  John Nantz ,  Ronald O. King

    发明人： Riad Ghabra ,  Yi Luo ,  John Nantz ,  Ronald O. King

    IPC分类号： B60R25/10

    CPC分类号： G07C9/00309 ,  B60R25/24 ,  G07C2009/00555 ,  G07C2009/00793

    摘要： An apparatus and method is provided for identifying unauthorized access to a vehicle having a keyless-passive entry system. An interrogation signal is broadcast from a vehicle based transmission device. The interrogation signal includes a first pulse transmitted at a first amplitude and a second pulse transmitted at a second amplitude where the second amplitude is greater than the first amplitude by at least a predetermined difference threshold. The interrogation signal is received by a portable communication device. A determination is made whether the second amplitude of the second pulse is greater than the first amplitude of the first pulse by a predetermined difference threshold. A determination is made that the interrogation signal is an authorized interrogation signal in response to the determination that the interrogation signal includes the first pulse transmitted at the first amplitude following by the second pulse transmitted at the second amplitude where the second amplitude is greater than the first amplitude by at least a predetermined difference threshold.

    摘要翻译： 提供了一种用于识别对具有无钥匙无源进入系统的车辆的未授权访问的装置和方法。 从基于车辆的传输设备广播询问信号。 询问信号包括以第一幅度发送的第一脉冲和以第二幅度发送的第二脉冲，其中第二幅度大于第一幅度至少预定的差值阈值。 询问信号由便携式通信设备接收。 确定第二脉冲的第二幅度是否大于第一脉冲的第一幅度预定的差阈值。 响应于确定询问信号包括以第二幅度发送的第二脉冲后的第一幅度发送的第一脉冲的确定，询问信号是授权询问信号，其中第二幅度大于第一幅度 振幅至少预定的差值阈值。

    Method for making a system for selecting one wire from a plurality of wires
    45.
    发明授权
    Method for making a system for selecting one wire from a plurality of wires 失效
    制造用于从多条电线中选择一条电线的系统的方法

    公开(公告)号：US07169696B2

    公开(公告)日：2007-01-30

    申请号：US10875057

    申请日：2004-06-22

    申请人： James R. Heath ,  Yi Luo ,  Rob Beckman

    发明人： James R. Heath ,  Yi Luo ,  Rob Beckman

    IPC分类号： H01L21/4763

    CPC分类号： B82Y10/00 ,  G11C2213/81 ,  H01L21/84 ,  H01L27/10 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/4908 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for selecting nanometer-scaled devices. The method includes a plurality of semiconductor wires. Two adjacent semiconductor wires of the plurality of semiconductor wires are associated with a separation smaller than or equal to 100 nm. Additionally, the system includes a plurality of address lines. Each of the plurality of address lines includes a gate region and an inactive region and intersects the plurality of semiconductor wires at a plurality of intersections. The plurality of intersections includes a first intersection and second intersection. The first intersection is associated with the gate region, and the second intersection is associated with the inactive region.

    摘要翻译： 用于选择纳米级设备的系统和方法。 该方法包括多个半导体布线。 多个半导体线中的两个相邻的半导体线与小于或等于100nm的分离相关联。 另外，该系统包括多个地址线。 多个地址线中的每一个都包括一个栅极区域和一个无效区域，并且在多个交点处与多个半导体布线相交。 多个交点包括第一交叉点和第二交点。 第一个交叉点与门区域相关联，第二个交叉路口与非活动区域相关联。

    External bus arbitration technique for multicore DSP device
    47.
    发明授权
    External bus arbitration technique for multicore DSP device 有权
    多核DSP设备的外部总线仲裁技术

    公开(公告)号：US07006521B2

    公开(公告)日：2006-02-28

    申请号：US10007840

    申请日：2001-11-08

    申请人： Duy Q. Nguyen ,  Harland Glenn Hopkins ,  Jay B. Reimer ,  Yi Luo ,  Tai H. Nguyen ,  Kevin A. McGonagle

    发明人： Duy Q. Nguyen ,  Harland Glenn Hopkins ,  Jay B. Reimer ,  Yi Luo ,  Tai H. Nguyen ,  Kevin A. McGonagle

    IPC分类号： H04J3/02

    CPC分类号： G06F13/364

    摘要： A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems each include a processor core and a DMA controller. The XPORT arbiter arbitrates between the processor cores and between the DMA controllers, and further arbitrates between processor control or DMA control of the XPORT. Upon a request signal from a DMA controller, the XPORT arbiter asserts a hold signal to the processor cores. The processor cores respond by asserting a hold acknowledge signal. A processor core will delay the hold acknowledge signal until through with the XPORT. The arbiter, then asserts a grant signal to the DMA controller requesting access. The arbiter may assert a grant signal to a processor core requesting access. However, the processor core's access will be stalled as long as the hold signal is asserted.

    摘要翻译： 数字信号处理系统包括多个处理器子系统，外部输入/输出端口（XPORT）和XPORT仲裁器。 处理器子系统各自包括处理器核心和DMA控制器。 XPORT仲裁器在处理器内核和DMA控制器之间进行仲裁，并进一步对XPORT的处理器控制或DMA控制进行仲裁。 根据来自DMA控制器的请求信号，XPORT仲裁器向处理器核心发出保持信号。 处理器核心通过置位保持确认信号来响应。 处理器内核将延迟保持确认信号，直到通过XPORT。 仲裁器然后向DMA控制器发出授权信号请求访问。 仲裁器可以向请求访问的处理器核心断言授权信号。 但是，只要保持信号有效，处理器核心的访问将被停止。

    Multicore DSP device having shared program memory with conditional write protection
    49.
    发明授权
    Multicore DSP device having shared program memory with conditional write protection 有权
    具有具有条件写保护功能的共享程序存储器的多核DSP设备

    公开(公告)号：US06895479B2

    公开(公告)日：2005-05-17

    申请号：US10008515

    申请日：2001-11-08

    申请人： Jay B. Reimer ,  Tai H. Nguyen ,  Yi Luo ,  Harland Glenn Hopkins ,  Dan K. Bui ,  Kevin A. McGonagle

    发明人： Jay B. Reimer ,  Tai H. Nguyen ,  Yi Luo ,  Harland Glenn Hopkins ,  Dan K. Bui ,  Kevin A. McGonagle

    IPC分类号： G06F12/14 ,  G06F9/00 ,  G06F11/00 ,  G06F11/26 ,  G06F12/00 ,  G06F15/177

    CPC分类号： G06F12/1433 ,  G06F11/2242 ,  G06F12/1491

    摘要： A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e.g., whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals. Each instruction bus read/write signal is preferably generated by a logic gate that prevents the processor core from affecting the read/write signal value in normal mode, but allows the processor core to determine the read/write signal value in emulation mode. In this manner, the logic gate prevents write operations to the shared program memory when the emulation logic de-asserts a signal indicative of emulation mode, and allows write operations to the shared program memory when the emulation logic asserts the signal indicative of emulation mode. The logic gate is preferably included in a bus interface module in each processor core.

    摘要翻译： 公开了具有具有条件写保护的共享程序存储器的多核数字信号处理器。 在一个实施例中，数字信号处理器包括共享程序存储器，仿真逻辑模块和多个处理器内核，每个核心通过相应的指令总线耦合到共享程序存储器。 仿真逻辑模块优选地确定每个处理器的操作模式，例如，它们是以正常模式还是仿真模式操作。 在仿真模式下，仿真逻辑可以改变各种处理器硬件的状态以及各种寄存器和存储器的内容。 指令总线各自包括读/写信号，其在相应的处理器核处于正常模式的同时被保持在读取状态。 另一方面，当处理器核心处于仿真模式时，允许处理器核心确定指令总线读/写信号的状态。 每个指令总线读/写信号优选地由逻辑门产生，该逻辑门防止处理器核在正常模式下影响读/写信号值，但允许处理器核确定仿真模式中的读/写信号值。 以这种方式，当仿真逻辑取消断言指示仿真模式的信号时，逻辑门防止对共享程序存储器的写操作，并且当仿真逻辑断言指示仿真模式的信号时，允许对共享程序存储器的写操作。 逻辑门优选地包括在每个处理器核心中的总线接口模块中。