公开(公告)号：US07006521B2

公开(公告)日：2006-02-28

申请号：US10007840

申请日：2001-11-08

申请人： Duy Q. Nguyen ,  Harland Glenn Hopkins ,  Jay B. Reimer ,  Yi Luo ,  Tai H. Nguyen ,  Kevin A. McGonagle

发明人： Duy Q. Nguyen ,  Harland Glenn Hopkins ,  Jay B. Reimer ,  Yi Luo ,  Tai H. Nguyen ,  Kevin A. McGonagle

IPC分类号： H04J3/02

CPC分类号： G06F13/364

摘要： A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems each include a processor core and a DMA controller. The XPORT arbiter arbitrates between the processor cores and between the DMA controllers, and further arbitrates between processor control or DMA control of the XPORT. Upon a request signal from a DMA controller, the XPORT arbiter asserts a hold signal to the processor cores. The processor cores respond by asserting a hold acknowledge signal. A processor core will delay the hold acknowledge signal until through with the XPORT. The arbiter, then asserts a grant signal to the DMA controller requesting access. The arbiter may assert a grant signal to a processor core requesting access. However, the processor core's access will be stalled as long as the hold signal is asserted.

摘要翻译： 数字信号处理系统包括多个处理器子系统，外部输入/输出端口（XPORT）和XPORT仲裁器。 处理器子系统各自包括处理器核心和DMA控制器。 XPORT仲裁器在处理器内核和DMA控制器之间进行仲裁，并进一步对XPORT的处理器控制或DMA控制进行仲裁。 根据来自DMA控制器的请求信号，XPORT仲裁器向处理器核心发出保持信号。 处理器核心通过置位保持确认信号来响应。 处理器内核将延迟保持确认信号，直到通过XPORT。 仲裁器然后向DMA控制器发出授权信号请求访问。 仲裁器可以向请求访问的处理器核心断言授权信号。 但是，只要保持信号有效，处理器核心的访问将被停止。

公开(公告)号：US06892266B2

公开(公告)日：2005-05-10

申请号：US10008696

申请日：2001-11-08

申请人： Jay B. Reimer ,  Harland Glenn Hopkins ,  Tai H. Nguyen ,  Yi Luo ,  Kevin A. McGonagle ,  Jason A. Jones ,  Duy Q. Nguyen ,  Patrick J. Smith

发明人： Jay B. Reimer ,  Harland Glenn Hopkins ,  Tai H. Nguyen ,  Yi Luo ,  Kevin A. McGonagle ,  Jason A. Jones ,  Duy Q. Nguyen ,  Patrick J. Smith

IPC分类号： G06F9/30 ,  G06F13/16 ,  G06F13/28 ,  G06F13/362 ,  G06F15/78 ,  G06F13/14

CPC分类号： G06F13/28

摘要： A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

摘要翻译： 公开了具有多个DMA控制器的DSP设备，其全局DMA访问DSP设备中的所有易失性存储器资源。 在优选实施例中，每个DMA控制器耦合到每个存储器总线，并且被配置为控制每个存储器总线。 存储器总线多路复用器可以耦合在子系统存储器总线和每个DMA控制器之间，并且仲裁器可以用于设置存储器总线多路复用器，以便允许任何一个DMA控制器来控制存储器总线。 存储器总线也可以经由存储器总线多路复用器由主机端口接口来控制。 循环仲裁技术用于提供每个控制器和主机端口接口公平地访问存储器总线。 这种方法可以有利地提供使用DMA控制器将数据从一个地方传输到另一个地方的增加的灵活性，只有最小的复杂性增加。

公开(公告)号：US06895479B2

公开(公告)日：2005-05-17

申请号：US10008515

申请日：2001-11-08

申请人： Jay B. Reimer ,  Tai H. Nguyen ,  Yi Luo ,  Harland Glenn Hopkins ,  Dan K. Bui ,  Kevin A. McGonagle

发明人： Jay B. Reimer ,  Tai H. Nguyen ,  Yi Luo ,  Harland Glenn Hopkins ,  Dan K. Bui ,  Kevin A. McGonagle

IPC分类号： G06F12/14 ,  G06F9/00 ,  G06F11/00 ,  G06F11/26 ,  G06F12/00 ,  G06F15/177

CPC分类号： G06F12/1433 ,  G06F11/2242 ,  G06F12/1491

摘要： A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e.g., whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals. Each instruction bus read/write signal is preferably generated by a logic gate that prevents the processor core from affecting the read/write signal value in normal mode, but allows the processor core to determine the read/write signal value in emulation mode. In this manner, the logic gate prevents write operations to the shared program memory when the emulation logic de-asserts a signal indicative of emulation mode, and allows write operations to the shared program memory when the emulation logic asserts the signal indicative of emulation mode. The logic gate is preferably included in a bus interface module in each processor core.

摘要翻译： 公开了具有具有条件写保护的共享程序存储器的多核数字信号处理器。 在一个实施例中，数字信号处理器包括共享程序存储器，仿真逻辑模块和多个处理器内核，每个核心通过相应的指令总线耦合到共享程序存储器。 仿真逻辑模块优选地确定每个处理器的操作模式，例如，它们是以正常模式还是仿真模式操作。 在仿真模式下，仿真逻辑可以改变各种处理器硬件的状态以及各种寄存器和存储器的内容。 指令总线各自包括读/写信号，其在相应的处理器核处于正常模式的同时被保持在读取状态。 另一方面，当处理器核心处于仿真模式时，允许处理器核心确定指令总线读/写信号的状态。 每个指令总线读/写信号优选地由逻辑门产生，该逻辑门防止处理器核在正常模式下影响读/写信号值，但允许处理器核确定仿真模式中的读/写信号值。 以这种方式，当仿真逻辑取消断言指示仿真模式的信号时，逻辑门防止对共享程序存储器的写操作，并且当仿真逻辑断言指示仿真模式的信号时，允许对共享程序存储器的写操作。 逻辑门优选地包括在每个处理器核心中的总线接口模块中。

公开(公告)号：US06691216B2

公开(公告)日：2004-02-10

申请号：US10004492

申请日：2001-10-24

申请人： Kenneth C. Kelly ,  Irvinderpal S. Ghai ,  Jay B. Reimer ,  Tai Huu Nguyen ,  Harland Glenn Hopkins ,  Yi Luo ,  Jason A. T. Jones ,  Dan K. Bui ,  Patrick J. Smith ,  Kevin A. McGonagle

发明人： Kenneth C. Kelly ,  Irvinderpal S. Ghai ,  Jay B. Reimer ,  Tai Huu Nguyen ,  Harland Glenn Hopkins ,  Yi Luo ,  Jason A. T. Jones ,  Dan K. Bui ,  Patrick J. Smith ,  Kevin A. McGonagle

IPC分类号： G06F1578

CPC分类号： G06F9/3802 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3891 ,  G06F15/786 ,  Y02D10/13

摘要： A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because each of the program cores typically executes the same software program, memory requirements may be reduced by having multiple processor cores share only a single copy of the software. Accordingly, a program memory couples to each of the processor cores by a corresponding instruction bus. Preferably the program memory services two or more instruction requests in each clock cycle. Data is preferably stored in separate memory arrays local to the processor core subsystems and accessible by the processor cores via a dedicated data bus. In one specific implementation, the program memory includes a wrapper that can perform one memory access in the first half of each clock cycle and a second memory access in the second half of each clock cycle. A designated set of instruction buses is allowed to arbitrate for only the first access, and the remaining instruction buses are allowed to arbitrate for only the second access. In this manner, a reduction in on-board memory requirements and associated power consumption may be advantageously reduced.

摘要翻译： 多核DSP设备包括共享程序存储器以消除冗余，从而减小DSP设备的尺寸和功耗。 由于每个程序内核通常执行相同的软件程序，因此可以通过使多个处理器核心共享该软件的单个副本来减少内存需求。 因此，程序存储器通过相应的指令总线耦合到每个处理器核心。 优选地，程序存储器在每个时钟周期中服务两个或更多个指令请求。 数据优选地存储在处理器核心子系统本地的分开的存储器阵列中，并且可经由专用数据总线由处理器核心访问。 在一个具体实现中，程序存储器包括一个包装器，其可以在每个时钟周期的前半部分中执行一个存储器访问，并且在每个时钟周期的后半部分中执行第二存储器访问。 允许指定的一组指令总线仅对第一次访问进行仲裁，并且允许剩余的指令总线仅对第二次访问进行仲裁。 以这种方式，可以有利地减少车载存储器要求的降低和相关联的功率消耗。

公开(公告)号：US07131114B2

公开(公告)日：2006-10-31

申请号：US10195640

申请日：2002-07-15

申请人： Tai H. Nguyen ,  Jay B. Reimer ,  H. Glenn Hopkins

发明人： Tai H. Nguyen ,  Jay B. Reimer ,  H. Glenn Hopkins

IPC分类号： G06F9/44 ,  G06F13/24

CPC分类号： G06F11/362

摘要： A processing system comprises a digital signal processor (DSP) device and a host system on which the DSP device is implemented. The DSP device comprises a shared program memory and a plurality of processor subsystems coupled to the shared program memory to concurrently execute program instructions stored in the shared program memory. The host system is capable of independently debugging each subsystem. During debugging, the host device inserts breakpoints into the shared program memory and tracks the debug breakpoints to determine which subsystems are associated with the breakpoints. When a subsystem executes a breakpoint associated with that subsystem, the subsystem halts until the host gathers necessary debug information from the subsystem. However, when a subsystem executes a breakpoint that is not associated with that subsystem, the host system causes the subsystem to execute the original program instructions and proceed as directed.

公开(公告)号：US07570646B2

公开(公告)日：2009-08-04

申请号：US09964158

申请日：2001-09-26

申请人： Martin Li ,  Jay B. Reimer ,  Shakuntala Anjanaiah ,  Natarajan Seshan ,  Patrick J. Smith

发明人： Martin Li ,  Jay B. Reimer ,  Shakuntala Anjanaiah ,  Natarajan Seshan ,  Patrick J. Smith

IPC分类号： H04L12/28

CPC分类号： G06F13/4004 ,  G06F1/24 ,  G06F13/28 ,  G06F13/385

摘要： A slave interface unit controls the exchange of data between a master processing unit and a plurality of slave processing units operating in the asynchronous transfer mode (ATM) of operation. The ATM slave interface unit has a receive unit and a transmit unit that exchange data cells and control signals with the ATM master processing unit. The receive unit and the transmit unit are coupled to a receive buffer storage unit and a transmit buffer storage unit, respectively. The receive buffer storage unit and the transmit buffer storage unit exchange data and control signals with the direct memory access unit. The ATM slave interface unit includes a configuration interface unit having a register that identifies the location in the data cell where the destination address is located and relates the destination address to the particular processing unit or memory location. The receive buffer unit uses the information in the register to determine the destination of the data cell.

摘要翻译： 从接口单元控制主处理单元和以异步传送模式（ATM）操作的多个从属处理单元之间的数据交换。 ATM从接口单元具有接收单元和与ATM主处理单元交换数据信元和控制信号的发送单元。 接收单元和发送单元分别耦合到接收缓冲存储单元和发送缓冲存储单元。 接收缓冲存储单元和发送缓冲存储单元与直接存储器存取单元交换数据和控制信号。 ATM从接口单元包括配置接口单元，其具有标识目的地址所在的数据单元中的位置的寄存器，并将目的地地址与特定处理单元或存储器位置相关联。 接收缓冲器单元使用寄存器中的信息来确定数据单元的目的地。

公开(公告)号：US07054958B2

公开(公告)日：2006-05-30

申请号：US10001153

申请日：2001-11-14

申请人： Ramesh A. Iyer ,  Henry D. Nguyen ,  Patrick J. Smith ,  Jay B. Reimer

发明人： Ramesh A. Iyer ,  Henry D. Nguyen ,  Patrick J. Smith ,  Jay B. Reimer

IPC分类号： G06F13/28

CPC分类号： G06F13/387

摘要： In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed. An abort signal is generated when a signal group for a packet being processed by the high level data link controller is not available in a timely manner.

公开(公告)号：US06959404B2

公开(公告)日：2005-10-25

申请号：US10202510

申请日：2002-07-24

申请人： Katsunobu Hirakawa ,  Weifeng Joe Zhou ,  Jay B. Reimer

发明人： Katsunobu Hirakawa ,  Weifeng Joe Zhou ,  Jay B. Reimer

IPC分类号： G06F1/04 ,  G06F11/00

CPC分类号： G06F11/0757

摘要： A data processor timer comprising a writeable control register, a look-up table and a loadable counter. The loadable counter operates in a first mode to load the count data field and operates in a second mode an entry from said look-up table specified by the count data field. The loadable counter generating a time out signal upon counting a number of clock pulses equal to said count. The writeable control register preferably includes a mode bit selecting the first or second modes. This invention is suitable for a pre-scalar counter as part of a data processor watchdog timer.

摘要翻译： 一种数据处理器定时器，包括可写控制寄存器，查找表和可加载计数器。 可加载计数器以第一模式操作以加载计数数据字段，并以第二模式操作来自由计数数据字段指定的查找表的条目。 可加载计数器在计数等于所述计数的时钟脉冲数时产生超时信号。 可写控制寄存器优选地包括选择第一或第二模式的模式位。 本发明适用于作为数据处理器看门狗定时器的一部分的预标量计数器。

公开(公告)号：US06823402B2

公开(公告)日：2004-11-23

申请号：US10001152

申请日：2001-11-14

申请人： Patrick J. Smith ,  Jay B. Reimer ,  Ramesh A. Iyer ,  Henry D. Nguyen

发明人： Patrick J. Smith ,  Jay B. Reimer ,  Ramesh A. Iyer ,  Henry D. Nguyen

IPC分类号： G06F1328

CPC分类号： G06F13/1652 ,  H04L29/06 ,  H04L69/324

摘要： In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem. In response to a predetermined condition, the signal groups are forwarded to the identified digital signal processor subsystem. The channel block unit, in response to preselected signal groups, can direct the packet to a digital signal processor subsystem that is different from the digital signal processor subsystem identified by the address signal group.

摘要翻译： 在包括多个数字信号处理器子系统的数据处理系统中，所选择的外围组件由数字信号处理器子系统共享。 特别地，高级数据链路控制器由子系统共享。 当共享高级数据链路控制器接收到分组时，数据信号组被处理并放置在临时存储单元中。 接收到的分组的地址信号组被应用于信道块单元，在该信道块单元中，识别分组被引导到的数字信号处理器子系统，并产生与所识别的数字信号处理器子系统对应的INTERRUPT信号。 INTERRUPT信号被应用于开关。 从临时存储单元接收信号组的开关将信号组引导到与所识别的信号处理子系统相关联的信道中的缓冲存储器。 响应于预定条件，信号组被转发到所识别的数字信号处理器子系统。 响应于预选信号组，信道块单元可以将分组引导到与由地址信号组识别的数字信号处理器子系统不同的数字信号处理器子系统。

公开(公告)号：US4802223A

公开(公告)日：1989-01-31

申请号：US548262

申请日：1983-11-03

申请人： Kun-Shan Lin ,  Jay B. Reimer

发明人： Kun-Shan Lin ,  Jay B. Reimer

IPC分类号： G10L19/00 ,  G10L19/04 ,  G10L5/00

CPC分类号： G10L19/0018

摘要： The present invention is a speech encoding technique useful in low data rate speech. Spoken input is analyzed to determine its basic phonological linguistic units and syllables. The pitch track for each syllable is compared with each of a predetermined set of pitch patterns. A pitch pattern forming the best match to the actual pitch track is selected for each syllable. Phonological linguistic unit indicia and pitch pattern indicia are transmitted to a speech synthesis apparatus. This synthesis apparatus matches the pitch pattern indicia to syllable groupings of the phonological linguistic unit indicia. During speech synthesis, sounds are produced corresponding to the phonological linguistic unit indicia with their primary pitch controlled by the pitch pattern indicia of the corresponding syllable. This achieves some measure of approximation to the primary pitch of the original spoken input at a low data rate. In the preferred embodiment, each pitch pattern includes an initial pitch slope, which may be zero indicating no change in pitch, a final pitch slope and a turning point between these two slopes.

摘要翻译： 本发明是一种在低数据速率语音中有用的语音编码技术。 分析口语输入，以确定其基本语音语言单位和音节。 将每个音节的音高轨道与预定的一组音调图案中的每一个进行比较。 为每个音节选择与实际音高音轨形成最佳匹配的音调图案。 语音语言单元标记和音调模式标记被传送到语音合成装置。 该合成装置将音调模式标记与语音语言单位标记的音节分组相匹配。 在语音合成期间，声音产生对应于语音语言单位标记，其主音调由相应音节的音调模式标记控制。 这实现了在低数据速率下对原始语音输入的主音高的一些近似度量。 在优选实施例中，每个俯仰图案包括初始俯仰斜率，其可以为零，表示在俯仰之间没有变化，最终俯仰斜率和转折点之间。