公开(公告)号：US09568601B1

公开(公告)日：2017-02-14

申请号：US14286937

申请日：2014-05-23

Applicant: Innophase Inc.

Inventor： Yang Xu ,  Nicolo Testi ,  Yuanwei Jin

IPC: G01S13/42 ,  G01S13/58 ,  G01S7/35

CPC classification number: G01S13/584 ,  G01S13/38 ,  G01S2007/358

Abstract: Determining a speed and a range of an object by generating at least a first, second, and third interval-specific tone phase signals associated with at least three successive time intervals, wherein at least two of the generated and transmitted tones are different frequencies; determining at least a first, second and third interval-specific average phase value from the respective interval-specific tone phase signals; and then determining a range estimate of the object and determining a speed estimate of the object using at least two phase differences between the at least first, second and third interval-specific average phase values.

Abstract translation: 通过产生与至少三个连续时间间隔相关联的至少第一，第二和第三区间特定的音调相位信号来确定对象的速度和范围，其中所生成和发送的音调中的至少两个是不同的频率; 从各个间隔特定的音调相位信号确定至少第一，第二和第三间隔特定平均相位值; 然后使用所述至少第一，第二和第三间隔特定平均相位值之间的至少两个相位差来确定所述对象的范围估计并确定所述对象的速度估计。

公开(公告)号：US09391625B1

公开(公告)日：2016-07-12

申请号：US14667368

申请日：2015-03-24

Applicant: Innophase, Inc.

Inventor： Yang Xu ,  Fa Foster Dai ,  Dongyi Liao

IPC: H03L7/06 ,  H03L7/099

CPC classification number: H03L7/0992 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095

Abstract: A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase input signal, unwraps the wrapped-phase input signal to generate an unwrapped-phase signal, and differentiates the unwrapped-phase signal. The wrapped-phase input signal and the differentiated unwrapped-phase signal are both injected into a feedback loop of the modulator circuit. The feedback loop may include a multi-modulus frequency divider with a frequency divisor that is temporarily incremented or decremented to cancel out abrupt phase jumps associated with the wrapped-phase to unwrapped-phase conversion.

Abstract translation: 数字控制振荡器（DCO）调制装置和方法提供宽带相位调制信号输出。 示例性调制器电路在锁相环中使用振荡器。 电路接收缠绕相输入信号，展开包络相输入信号以产生展开相位信号，并对展开相位信号进行微分。 包络相输入信号和微分解包相位信号都被注入到调制器电路的反馈回路中。 反馈回路可以包括具有暂时增加或减小的频率除数的多模式分频器，以消除与包绕相位相关的突变相位跳变到展开相位转换。

公开(公告)号：US09319052B2

公开(公告)日：2016-04-19

申请号：US14275477

申请日：2014-05-12

Applicant: Innophase Inc.

Inventor： Yang Xu ,  Sara Munoz Hermoso

IPC: H03L7/099 ,  H04L27/227 ,  H03L7/085 ,  H03B5/12 ,  H03D5/00

CPC classification number: H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B2200/0074 ,  H03D5/00 ,  H03L7/085 ,  H04L27/227 ,  H04L27/2272

Abstract: A receiver includes a harmonic injection-locked oscillator, which receives an RF modulated signal and provides an output to two parallel signal paths. A fundamental injection-locked oscillator is provided on one of the signal paths. A phase discriminator detects a phase difference between signals that have passed through the first and second signal paths. At least one of the signal paths includes an amplitude limiting circuit. One or more of the signal paths may include an adjustable delay circuit.

Abstract translation: 接收机包括谐波注入锁定振荡器，其接收RF调制信号并向两个并行信号路径提供输出。 在其中一个信号路径上提供基本的注入锁定振荡器。 相位鉴别器检测已经通过第一和第二信号路径的信号之间的相位差。 至少一个信号路径包括限幅电路。 一个或多个信号路径可以包括可调延迟电路。

公开(公告)号：US20160087645A1

公开(公告)日：2016-03-24

申请号：US14955963

申请日：2015-12-01

Applicant: Innophase, Inc.

Inventor： Xuejun Zhang ,  Yang Xu

IPC: H03M3/00 ,  H03M1/74 ,  G05F3/26

CPC classification number: H03M3/50 ,  G05F1/625 ,  G05F3/262 ,  H03F3/04 ,  H03M1/00 ,  H03M1/002 ,  H03M1/0854 ,  H03M1/742 ,  H03M1/747

Abstract: A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current.

公开(公告)号：US09031167B2

公开(公告)日：2015-05-12

申请号：US13754841

申请日：2013-01-30

Applicant: Innophase Inc.

Inventor： Yang Xu

IPC: H03D3/18 ,  H04L27/227 ,  H04L27/20 ,  H04L27/22

CPC classification number: H04L27/2272 ,  H04L27/2071 ,  H04L27/22

Abstract: A receiver is described. The receiver includes a filter configured to receive a quadrature phase shift keying (“QPSK”) signal. Further, the receiver includes an amplifier coupled with the filter. And, a QPSK decomposition filter is coupled with the amplifier. The QPSK decomposition filter is configured to generate a first BPSK signal based on the QPSK signal and a second BPSK signal based on the QPSK signal.

Abstract translation: 描述接收机。 接收机包括被配置为接收正交相移键控（“QPSK”）信号的滤波器。 此外，接收机包括与滤波器耦合的放大器。 并且，QPSK分解滤波器与放大器耦合。 QPSK分解滤波器被配置为基于QPSK信号和基于QPSK信号的第二BPSK信号生成第一BPSK信号。

公开(公告)号：US08929486B2

公开(公告)日：2015-01-06

申请号：US13840478

申请日：2013-03-15

Applicant: Innophase, Inc.

Inventor： Yang Xu ,  Sara Munoz Hermoso

IPC: H03D3/18 ,  H03D3/00 ,  H04L27/227

CPC classification number: H03D3/007 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03D1/22 ,  H03D5/00 ,  H04L27/227 ,  H04L27/2272 ,  H04L27/389

Abstract: Compressing a variable phase component of a received modulated signal with a second harmonic injection locking oscillator, and generating a delayed phase-compressed signal with a fundamental injection locking oscillator, and combining the phase-compressed signal and the delayed phase-compressed signal to obtain an estimated derivative of the variable phase component, and further processing the estimated derivative to recover data contained within the received modulated signal.

Abstract translation: 用二次谐波注入锁定振荡器压缩接收到的调制信号的可变相位分量，并用基本注入锁定振荡器产生延迟相位压缩信号，并组合相位压缩信号和延迟相位压缩信号以获得 估计的可变相位分量的导数，并且进一步处理估计的导数以恢复包含在接收的调制信号内的数据。

公开(公告)号：US08804875B1

公开(公告)日：2014-08-12

申请号：US13925080

申请日：2013-06-24

Applicant: Innophase Inc.

Inventor： Yang Xu ,  Sara Munoz Hermoso

IPC: H03D3/18 ,  H04L27/227

CPC classification number: H03D3/007 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03D1/22 ,  H03D5/00 ,  H04L27/227 ,  H04L27/2272 ,  H04L27/389

Abstract: Compressing a variable phase component of a received modulated signal with a second harmonic injection locking oscillator, and generating a delayed phase-compressed signal with a fundamental injection locking oscillator, and combining the phase-compressed signal and the delayed phase-compressed signal to obtain an estimated derivative of the variable phase component, and further processing the estimated derivative to recover data contained within the received modulated signal.

Abstract translation: 用二次谐波注入锁定振荡器压缩接收到的调制信号的可变相位分量，并用基本注入锁定振荡器产生延迟相位压缩信号，并组合相位压缩信号和延迟相位压缩信号以获得 估计的可变相位分量的导数，并且进一步处理估计的导数以恢复包含在接收的调制信号内的数据。

公开(公告)号：US20140023163A1

公开(公告)日：2014-01-23

申请号：US14034426

申请日：2013-09-23

Applicant: Innophase Inc.

Inventor： Yang Xu

IPC: H04L27/227

CPC classification number: H04L27/2272 ,  H04L27/2071 ,  H04L27/22

Abstract: A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.

Abstract translation: 描述接收机。 接收机包括第一注入锁定振荡器，其具有被配置为接收BPSK信号的第一输入和被配置为接收第一频率参考的第二输入。 接收机还包括第二注入锁定振荡器，其具有被配置为接收BPSK信号的第三输入和被配置为接收第二频率参考的第四输入。 此外，接收机包括与第一注入锁定振荡器的第二输入耦合的第一锁相环。 第一锁相环被配置为产生第一频率参考。 并且，第二锁相环与第二注入锁定振荡器的第四输入耦合。 第二锁相环被配置为产生第二频率参考。

公开(公告)号：US20130195224A1

公开(公告)日：2013-08-01

申请号：US13754841

申请日：2013-01-30

Applicant: Innophase Inc.

Inventor： Yang Xu

IPC: H04L27/22

CPC classification number: H04L27/2272 ,  H04L27/2071 ,  H04L27/22

Abstract: A receiver is described. The receiver includes a filter configured to receive a quadrature phase shift keying (“QPSK”) signal. Further, the receiver includes an amplifier coupled with the filter. And, a QPSK decomposition filter is coupled with the amplifier. The QPSK decomposition filter is configured to generate a first BPSK signal based on the QPSK signal and a second BPSK signal based on the QPSK signal.

Abstract translation: 描述接收机。 接收机包括被配置为接收正交相移键控（“QPSK”）信号的滤波器。 此外，接收机包括与滤波器耦合的放大器。 并且，QPSK分解滤波器与放大器耦合。 QPSK分解滤波器被配置为基于QPSK信号和基于QPSK信号的第二BPSK信号生成第一BPSK信号。

公开(公告)号：US20240007264A1

公开(公告)日：2024-01-04

申请号：US18346189

申请日：2023-06-30

Applicant: Innophase, Inc.

Inventor： Claudio Anzil ,  Yang Xu ,  Farhad Zarkeshvari

IPC: H04L7/04 ,  H04L27/36 ,  H04B7/06

CPC classification number: H04L7/04 ,  H04L27/361 ,  H04B7/0691

Abstract: Transceiver array synchronization by receiving a clock signal and at least one synchronization pulse signal at each transceiver IC of a plurality of transceiver integrated circuit (IC) subarrays, wherein each transceiver IC subarray contains a respective set of serially connected transceiver ICs; and synchronizing the transceiver IC with other transceiver ICs of the respective set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal.