中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

77 records (took 0.023 seconds)

    PACKET PROCESSING WITH REDUCED LATENCY
    41.
    发明公开
    PACKET PROCESSING WITH REDUCED LATENCY 审中-公开

    公开(公告)号：US20230421512A1

    公开(公告)日：2023-12-28

    申请号：US18243896

    申请日：2023-09-08

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Jesse C. Brandeburg ,  Anil Vasudevan

    IPC: H04L49/90 ,  G06F9/48 ,  G06F9/52 ,  H04L49/901

    CPC classification number: H04L49/90 ,  G06F9/4812 ,  G06F9/526 ,  H04L49/901 ,  G06F9/327

    Abstract: Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

    PACKET PROCESSING WITH REDUCED LATENCY
    45.
    发明申请
    PACKET PROCESSING WITH REDUCED LATENCY 有权

    公开(公告)号：US20220038395A1

    公开(公告)日：2022-02-03

    申请号：US17505443

    申请日：2021-10-19

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Jesse C. Brandeburg ,  Anil Vasudevan

    IPC: H04L12/861 ,  G06F9/48 ,  G06F9/52 ,  H04L12/879

    Abstract: Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

    SOFTWARE-DEFINED NETWORKING DATA RE-DIRECTION
    46.
    发明申请
    SOFTWARE-DEFINED NETWORKING DATA RE-DIRECTION 有权

    公开(公告)号：US20210385720A1

    公开(公告)日：2021-12-09

    申请号：US17184832

    申请日：2021-02-25

    Applicant: Intel Corporation

    Inventor： Jonas Svennebring ,  Niall D. McDonnell ,  Andrey Chilikin ,  Andrew Cunningham ,  Christopher MacNamara ,  Carl-Oscar Montelius ,  Eliezer Tamir ,  Bjorn Topel

    IPC: H04W36/30 ,  H04W36/32 ,  H04L12/715 ,  H04W76/27 ,  H04L12/717 ,  H04W40/18

    Abstract: Aspects of data re-direction are described, which can include software-defined networking (SDN) data re-direction operations. Some aspects include data re-direction operations performed by one or more virtualized network functions. In some aspects, a network router decodes an indication of a handover of a user equipment (UE) from a first end point (EP) to a second EP, based on the indication, the router can update a relocation table including the UE identifier, an identifier of the first EP, and an identifier of the second EP. The router can receive a data packet for the UE, configured for transmission to the first EP, and modify the data packet, based on the relocation table, for rerouting to the second EP. In some aspects, the router can decode handover prediction information, including an indication of a predicted future geographic location of the UE, and update the relocation table based on the handover prediction information.

    Packet processing with reduced latency
    47.
    发明授权
    Packet processing with reduced latency 有权

    公开(公告)号：US11178076B2

    公开(公告)日：2021-11-16

    申请号：US16577406

    申请日：2019-09-20

    Applicant: INTEL CORPORATION

    Inventor： Eliezer Tamir ,  Jesse C. Brandeburg ,  Anil Vasudevan

    IPC: H04L12/861 ,  H04L12/879 ,  G06F9/48 ,  G06F9/52 ,  G06F9/448 ,  G06F9/32

    Abstract: Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

    Systems and methods for multi-architecture computing
    50.
    发明授权
    Systems and methods for multi-architecture computing 有权

    公开(公告)号：US10713213B2

    公开(公告)日：2020-07-14

    申请号：US15386919

    申请日：2016-12-21

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman

    IPC: G06F9/44 ,  G06F9/45 ,  G06F9/445 ,  G06F15/80 ,  G06F8/41

    Abstract: Systems and methods for multi-architecture computing. Some computing devices may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

Patent Agency Ranking