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公开(公告)号：US20170250892A1
公开(公告)日：2017-08-31
申请号：US15056570
申请日：2016-02-29
申请人： Intel Corporation
发明人： Trevor Cooper , Kapil Sood , Scott P. Dubal , Michael Hingston McLaughlin Bursell , Jesse C. Brandeburg , Stephen T. Palermo
CPC分类号： G06F21/44 , G06F21/552 , H04L41/5009 , H04L41/5019
摘要： Technologies for monitoring service level agreement (SLA) performance in an end-to-end SLA monitoring architecture include a network functions virtualization (NFV) SLA controller configured to manage SLA agents initialized in various network processing components of the end-to-end SLA monitoring architecture. To do so, the NFV SLA controller is configured to provide instruction to the SLA agents indicating which types of telemetry data to monitor and receive the requested telemetry data, as securely collected and securely packaged by the SLA agents. The NFV SLA controller is further configured to securely analyze the received telemetry data to determine one or more performance metrics and compare performance benchmarks against the performance metrics to generate an SLA report that includes the results of the comparison. Other embodiments are described and claimed.
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公开(公告)号：US10572650B2
公开(公告)日：2020-02-25
申请号：US15056570
申请日：2016-02-29
申请人： Intel Corporation
发明人： Trevor Cooper , Kapil Sood , Scott P. Dubal , Michael Hingston McLaughlin Bursell , Jesse C. Brandeburg , Stephen T. Palermo
摘要： Technologies for monitoring service level agreement (SLA) performance in an end-to-end SLA monitoring architecture include a network functions virtualization (NFV) SLA controller configured to manage SLA agents initialized in various network processing components of the end-to-end SLA monitoring architecture. To do so, the NFV SLA controller is configured to provide instruction to the SLA agents indicating which types of telemetry data to monitor and receive the requested telemetry data, as securely collected and securely packaged by the SLA agents. The NFV SLA controller is further configured to securely analyze the received telemetry data to determine one or more performance metrics and compare performance benchmarks against the performance metrics to generate an SLA report that includes the results of the comparison. Other embodiments are described and claimed.
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公开(公告)号：US09985886B2
公开(公告)日：2018-05-29
申请号：US14671776
申请日：2015-03-27
申请人： Intel Corporation
IPC分类号： H04L12/801 , H04L12/26 , H04L12/805
CPC分类号： H04L47/12 , H04L43/0864 , H04L47/36
摘要： Technologies for pacing transmission of network packets by a computing device to a remote computing device include performing a segmentation offload operation to segment a payload of a network packet into a plurality of network packet segments in response to a determination that a size of the payload is greater than a maximum allowable payload size. The computing device additionally determines a packet pacing interval and transmits the plurality of network packet segments to the remote computing device at a transmission rate based on the packet pacing interval.
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公开(公告)号：US10158585B2
公开(公告)日：2018-12-18
申请号：US13773255
申请日：2013-02-21
申请人： INTEL CORPORATION
IPC分类号： H04L12/861 , G06F9/48 , G06F9/52 , G06F9/32 , H04L12/879 , G06F9/448
摘要： Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.
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公开(公告)号：US10127072B2
公开(公告)日：2018-11-13
申请号：US15874266
申请日：2018-01-18
申请人： Intel Corporation
发明人： Stephen T. Palermo , Scott P. Dubal , Trevor Cooper , Anjali S. Jain , Iosif Gasparakis , Jr-Shian Tsai , Mike Bursell , Pradeepsunder Ganesh , Parthasarathy Sarangam , Jesse C. Brandeburg
摘要： The present disclosure is directed to enhanced virtual function capabilities in a virtualized network environment. In general, devices may comprise physical and virtualized resources. The physical resources may comprise at least a network adaptor that may handle incoming data from a network and outgoing data to the network. The virtualized resources may comprise at least one virtual machine (VM) and a corresponding interface. The corresponding interface may be one of a physical interface, a virtual interface or a “super” virtual interface. The physical interface may provide a first set of capabilities allowing the VM to access (e.g., control) at least the network adaptor. The virtual interface may provide a second set of capabilities that is a subset of the first set. The super virtual interface may provide a third set of capabilities including the second set of capabilities and at least one additional capability from the first set of capabilities.
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公开(公告)号：US10048977B2
公开(公告)日：2018-08-14
申请号：US14978569
申请日：2015-12-22
申请人： Intel Corporation
发明人： Stephen T. Palermo , Thomas E. Willis , Kapil Sood , Ilango S. Ganga , Scott P. Dubal , Pradeepsunder Ganesh , Jesse C. Brandeburg
IPC分类号： G06F9/455 , H04L12/931
摘要： Methods and Apparatus for Multi-Stage VM Virtual Network Function and Virtual Service Function Chain Acceleration for NFV and needs-based hardware acceleration. Compute platform hosting virtualized environments including virtual machines (VMs) running service applications performing network function virtualization (NFV) employ Field Programmable Gate Array (FPGA) to provide a hardware-based fast path for performing VM-to-VM and NFV-to-NFV transfers. The FPGAs, along with associated configuration data are also configured to support dynamic assignment and performance of hardware-acceleration to offload processing tasks from processors in virtualized environments, such as cloud data centers and the like.
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公开(公告)号：US10476818B2
公开(公告)日：2019-11-12
申请号：US15400629
申请日：2017-01-06
申请人： Intel Corporation
IPC分类号： H04L12/861 , H04L12/879 , G06F9/48 , G06F9/52 , G06F9/448 , G06F9/32
摘要： Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.
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公开(公告)号：US10178054B2
公开(公告)日：2019-01-08
申请号：US15088910
申请日：2016-04-01
申请人： INTEL CORPORATION
发明人： Stephen T. Palermo , Iosif Gasparakis , Scott P. Dubal , Kapil Sood , Trevor Cooper , Jr-Shian Tsai , Jesse C. Brandeburg , Andrew J. Herdrich , Edwin Verplanke
IPC分类号： H04L12/861 , H04L12/715 , H04L12/931 , G06F15/173
摘要： Methods and apparatus for accelerating VM-to-VM Network Traffic using CPU cache. A virtual queue manager (VQM) manages data that is to be kept in VM-VM shared data buffers in CPU cache. The VQM stores a list of VM-VM allow entries identifying data transfers between VMs that may use VM-VM cache “fast-path” forwarding. Packets are sent from VMs to the VQM for forwarding to destination VMs. Indicia in the packets (e.g., in a tag or header) is inspected to determine whether a packet is to be forwarded via a VM-VM cache fast path or be forwarded via a virtual switch. The VQM determines the VM data already in the CPU cache domain while concurrently coordinating with the data to and from the external shared memory, and also ensures data coherency between data kept in cache and that which is kept in shared memory.
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公开(公告)号：US20230421512A1
公开(公告)日：2023-12-28
申请号：US18243896
申请日：2023-09-08
申请人： Intel Corporation
IPC分类号： H04L49/90 , G06F9/48 , G06F9/52 , H04L49/901
CPC分类号： H04L49/90 , G06F9/4812 , G06F9/526 , H04L49/901 , G06F9/327
摘要： Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.
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公开(公告)号：US11843550B2
公开(公告)日：2023-12-12
申请号：US17505443
申请日：2021-10-19
申请人： Intel Corporation
CPC分类号： H04L49/90 , G06F9/4812 , G06F9/526 , H04L49/901 , G06F9/327 , G06F9/4498
摘要： Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.
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