公开(公告)号：US20210136680A1

公开(公告)日：2021-05-06

申请号：US17119698

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： John J. Browne ,  Chris M. MacNamara ,  David Hunt ,  Amruta Misra ,  Tomasz Kantecki ,  Shobhi Jain ,  Liang Ma

IPC: H04W52/02 ,  H04L12/24

Abstract: A system comprising an interface to access a network slice power consumption parameter for a network slice comprising a logical network between two endpoints through a plurality of physical computing platforms; and a controller comprising circuitry, the controller to specify operating parameters for a plurality of hardware resources of a first physical computing platform in accordance with the network slice power consumption parameter.

公开(公告)号：US10936449B2

公开(公告)日：2021-03-02

申请号：US15465247

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Hang T. Nguyen ,  Stephen T. Palermo ,  John J. Browne ,  Chris MacNamara ,  Pradeepsunder Ganesh

IPC: G06F11/00 ,  G06F11/20 ,  G06F3/06 ,  G06F11/30

Abstract: Discussed herein are component redundancy systems, devices, and methods. A method to transfer a workload from a first component to a second component of a same device may include monitoring a wear indicator associated with the first component, and in response to an indication that the first component is stressed based on the wear indicator, transferring a workload of the first component to the second component.

公开(公告)号：US20210021484A1

公开(公告)日：2021-01-21

申请号：US17033557

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Kapil Sood ,  Timothy Verrall ,  Ned M. Smith ,  Tarun Viswanathan ,  Kshitij Doshi ,  Francesc Guim Bernat ,  John J. Browne ,  Katalin Bartfai-Walcott ,  Maryam Tahhan ,  Eoin Walsh ,  Damien Power

IPC: H04L12/24 ,  H04L29/06 ,  H04L12/26

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to schedule workloads based on secure edge to device telemetry by calculating a difference between a first telemetric data received from a first hardware device and an operating parameter and computing an adjustment for a second hardware device based on the difference between the first telemetric data and the operating parameter.

公开(公告)号：US10601738B2

公开(公告)日：2020-03-24

申请号：US16024774

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Bruce Richardson ,  Chris MacNamara ,  Patrick Fleming ,  Tomasz Kantecki ,  Ciara Loftus ,  John J. Browne ,  Patrick Connor

IPC: H04L12/861 ,  H04L12/879

Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.

公开(公告)号：US20190327190A1

公开(公告)日：2019-10-24

申请号：US16460424

申请日：2019-07-02

Applicant: Intel Corporation

Inventor： John J. Browne ,  Tomasz Kantecki ,  Chris MacNamara ,  Pierre Laurent ,  Sean Harte

IPC: H04L12/879 ,  H04L12/46 ,  H04L12/861 ,  H04L12/43 ,  H04L12/927 ,  H04L12/935

Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.

公开(公告)号：US20190097951A1

公开(公告)日：2019-03-28

申请号：US15719081

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Tomasz Kantecki ,  Niall Power ,  John J. Browne ,  Christopher MacNamara ,  Stephen Doyle

IPC: H04L12/861 ,  H04L12/883

Abstract: A network interface device, including: an ingress interface; a host platform interface to communicatively couple to a host platform; and a packet preprocessor including logic to: receive via the ingress interface a data sequence including a plurality of discrete data units; identify the data sequence as data for a parallel processing operation; reorder the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and send the reordered data to the host platform via the host platform interface.

公开(公告)号：US20190097948A1

公开(公告)日：2019-03-28

申请号：US15718836

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： John J. Browne ,  Christopher MacNamara ,  Tomasz Kantecki ,  Barak Hermesh ,  Sean Harte ,  Andrey Chilikin ,  Brendan Ryan ,  Bruce Richardson ,  Michael A. O'Hanlon ,  Andrew Cunningham

IPC: H04L12/935 ,  H04L12/861

Abstract: An apparatus, including: a hardware platform; logic to execute on the hardware platform, the logic configured to: receive a batch including first plurality of packets; identify a common attribute of the batch; perform batch processing on the batch according to the common attribute; generate a hint for the batch, the hint comprising information about the batch to facilitate processing of the batch; and forward the batch to a host platform network interface with the hint.

公开(公告)号：US20190042739A1

公开(公告)日：2019-02-07

申请号：US16022976

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： John J. Browne ,  Marcel Cornu ,  Timothy Verrall ,  Tomasz Kantecki ,  Niall Power ,  Weigang Li ,  Eoin Walsh ,  Maryam Tahhan

IPC: G06F21/55 ,  G06F21/56

Abstract: Technologies for cache side channel attack detection and mitigation include an analytics server and one or more monitored computing devices. The analytics server polls each computing device for analytics counter data. The computing device generates the analytics counter data using a resource manager of a processor of the computing device. The analytics counter data may include last-level cache data or memory bandwidth data. The analytics server identifies suspicious core activity based on the analytics counter data and, if identified, deploys a detection process to the computing device. The computing device executes the detection process to identify suspicious application activity. If identified, the computing device may perform one or more corrective actions. Corrective actions include limiting resource usage by a suspicious process using the resource manager of the processor. The resource manager may limit cache occupancy or memory bandwidth used by the suspicious process. Other embodiments are described and claimed.

公开(公告)号：US20190004922A1

公开(公告)日：2019-01-03

申请号：US15637706

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： John J. Browne ,  Tomasz Kantecki ,  Wojciech Andralojc ,  Timothy Verrall ,  Maryam Tahhan ,  Eoin Walsh ,  Damien Power ,  Chris Macnamara

IPC: G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3495 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/3017 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/88 ,  G06N5/045 ,  G06N20/00

Abstract: A method for monitoring health of processes includes a compute device having a performance monitoring parameter manager and an analytics engine. The compute device accesses performance monitoring parameters associated with a monitored process of the compute device. The compute device samples one or more hardware counters associated with the monitored process and applies a performance monitor filter to the sampled one or more hardware counters to generate hardware counter values. The compute device performs a process fault check on the monitored process based on the hardware counter values and the performance monitoring parameters.

公开(公告)号：US20180357099A1

公开(公告)日：2018-12-13

申请号：US15617375

申请日：2017-06-08

Applicant: Intel Corporation

Inventor： John J. Browne ,  Tomasz Kantecki ,  Eoin Walsh ,  Maryam Tahhan ,  Timothy Verrall ,  Tarun Viswanathan ,  Rory Browne

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/455

CPC classification number: G06F9/5005 ,  G06F9/45504 ,  G06F9/4881

Abstract: Particular embodiments described herein provide for a network element that can be configured to determine a pre-execution performance test, where the pre-execution performance test is at least partially based on requirements for a process to be executed, cause the pre-execution performance test to be executed on a platform before the process is executed on the platform, where the platform is a dynamically allocated group of resources, analyze results of the pre-execution performance test, and cause the process to be executed on the platform if the results of the pre-execution performance test satisfy a condition. In an example, the process is a virtual network function.