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    SYSTEMS AND METHODS FOR MESSAGE ASSURANCE IN VEHICLE SYSTEMS
    41.
    发明申请
    SYSTEMS AND METHODS FOR MESSAGE ASSURANCE IN VEHICLE SYSTEMS 审中-公开

    公开(公告)号：US20200226274A1

    公开(公告)日：2020-07-16

    申请号：US16833200

    申请日：2020-03-27

    Applicant: Intel Corporation

    Inventor： Marcio Juliato ,  Shabbir Ahmed ,  Maria Soledad Elli ,  Christopher Noe Gutierrez ,  Vuk Lesi ,  Manoj R. Sastry ,  John Charles Weast ,  Liuyang Lily Yang

    IPC: G06F21/62 ,  G06F13/38

    Abstract: A vehicle control system, including an in-vehicle bus and a plurality of electronic control units (ECUs) coupled to the in-vehicle bus, wherein at least one ECU of the plurality of ECUs is configured to: receive, at a respective at least one ECU of the plurality of ECUs, a message in a message stream on the in-vehicle bus; evaluate the message to determine at least one of a confidence value of the security classification, a significance value of the message, or a bounds check value of the message; and determine in real-time to allow or deny the message to the vehicle control system based on at least one of the significance value of the message, the bounds check value of the message, or the confidence value of the security classification of the message, to provide a sanitized message stream to the vehicle control system.

    TECHNOLOGIES FOR ROBUST COMPUTATION OF ELLIPTIC CURVE DIGITAL SIGNATURES
    42.
    发明申请
    TECHNOLOGIES FOR ROBUST COMPUTATION OF ELLIPTIC CURVE DIGITAL SIGNATURES 审中-公开

    公开(公告)号：US20200092112A1

    公开(公告)日：2020-03-19

    申请号：US16682635

    申请日：2019-11-13

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Manoj R. Sastry

    IPC: H04L9/32 ,  H04L9/30 ,  G09C1/00

    Abstract: Technologies for elliptic curve cryptography (ECC) include a computing device having an ECC engine that reads one or more parameters from a data port. The ECC engine performs operations using the parameters, such as an Elliptic Curve Digital Signature Algorithm (ECDSA). The ECDSA may be performed in a protected mode, in which the ECC engine will ignore inputs. The ECC engine may perform the ECDSA in a fixed amount of time in order to protect against timing side-channel attacks. The ECC engine may perform the ECDSA by consuming a uniform amount of power in order to protect against power side-channel attacks. The ECC engine may perform the ECDSA by emitting a uniform amount of electromagnetic radiation in order to protect against EM side-channel attacks. The ECC engine may perform the ECDSA verify with 384-bit output in order to protect against fault injection attacks.

    Authentication through voltage variations over communication channels
    43.
    发明授权
    Authentication through voltage variations over communication channels 有权

    公开(公告)号：US10355891B2

    公开(公告)日：2019-07-16

    申请号：US15720389

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Marcio Juliato ,  Li Zhao ,  Ahmed Shabbir ,  Manoj R. Sastry ,  Santosh Ghosh ,  Rafael Misoczki

    IPC: H04L12/40 ,  H04L25/49

    Abstract: Embodiments may include systems and methods for authenticating a message between a transmitter and a receiver. An apparatus for communication may include a transmitter to transmit a message to a receiver via a physical channel coupling the transmitter and the receiver. The message may be transmitted via a plurality of transmission voltage levels varied from a plurality of nominal voltage levels on the physical channel. The transmitter may include a voltage generator to generate the plurality of transmission voltage levels varied in accordance with a sequence of voltage variations from the plurality of nominal voltage levels for the message. The sequence of voltage variations may serve to authenticate the message between the transmitter and the receiver. Other embodiments may be described and/or claimed.

    Configurable crypto hardware engine
    44.
    发明授权
    Configurable crypto hardware engine 有权

    公开(公告)号：US10348495B2

    公开(公告)日：2019-07-09

    申请号：US15441030

    申请日：2017-02-23

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Rafael Misoczki ,  Manoj R. Sastry ,  Li Zhao

    IPC: H04L9/08 ,  H04L9/32 ,  H04L9/00 ,  H04L9/06

    Abstract: Apparatuses and methods associated with configurable crypto hardware engine are disclosed herein. In embodiments, an apparatus for signing or verifying a message may comprise: a hardware hashing computation block to perform hashing computations; a hardware hash chain computation block to perform successive hash chain computations; a hardware private key generator to generate private keys; and a hardware public key generator to generate public keys, including signature generations and signature verifications. The hardware hashing computation block, the hardware hash chain computation block, the hardware private key generator, and the hardware public key generator may be coupled to each other and selectively cooperate with each other to perform private key generation, public key generation, signature generation or signature verification at different points in time. Other embodiments may be disclosed or claimed.

    CONFIGURABLE CRYPTO HARDWARE ENGINE
    48.
    发明申请
    CONFIGURABLE CRYPTO HARDWARE ENGINE 审中-公开

    公开(公告)号：US20180241554A1

    公开(公告)日：2018-08-23

    申请号：US15441030

    申请日：2017-02-23

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Rafael Misoczki ,  Manoj R. Sastry ,  Li Zhao

    IPC: H04L9/08 ,  H04L9/32 ,  H04L9/30

    CPC classification number: H04L9/0861 ,  H04L9/002 ,  H04L9/0643 ,  H04L9/3236 ,  H04L9/3247 ,  H04L2209/12 ,  H04L2209/38

    Abstract: Apparatuses and methods associated with configurable crypto hardware engine are disclosed herein. In embodiments, an apparatus for signing or verifying a message may comprise: a hardware hashing computation block to perform hashing computations; a hardware hash chain computation block to perform successive hash chain computations; a hardware private key generator to generate private keys; and a hardware public key generator to generate public keys, including signature generations and signature verifications. The hardware hashing computation block, the hardware hash chain computation block, the hardware private key generator, and the hardware public key generator may be coupled to each other and selectively cooperate with each other to perform private key generation, public key generation, signature generation or signature verification at different points in time. Other embodiments may be disclosed or claimed.

    ULTRA-LIGHTWEIGHT CRYPTOGRAPHY ACCELERATOR SYSTEM
    49.
    发明申请
    ULTRA-LIGHTWEIGHT CRYPTOGRAPHY ACCELERATOR SYSTEM 审中-公开

    公开(公告)号：US20180183573A1

    公开(公告)日：2018-06-28

    申请号：US15392252

    申请日：2016-12-28

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Li Zhao ,  Rafael Misoczki ,  Manoj R. Sastry

    IPC: H04L9/06 ,  G06F21/72 ,  H04L9/32 ,  G06F1/32 ,  G06F13/28

    CPC classification number: H04L9/0618 ,  G06F1/3296 ,  G06F13/28 ,  G06F21/72 ,  H04L9/0643 ,  H04L9/3242 ,  Y02D10/14

    Abstract: A cryptography accelerator system includes a direct memory access (DMA) controller circuit to read and write data directly to and from memory circuits and an on-the-fly hashing circuit to hash data read from a first memory circuit on-the-fly before writing the read data to a second memory circuit. The hashing circuit performs at least one of integrity protection and firmware/software (FW/SW) verification of the data prior to writing the data to the second memory circuit. The on-the-fly hashing circuit includes a bit repositioning circuit to designate an order of bits of a binary word in a register from a most significant bit (MSB) to a least significant bit (LSB) for performing computations without rotating bits in the register, and an on-the-fly round constant generator circuit to generate a round constant from a counter.

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