公开(公告)号：US20150120035A1

公开(公告)日：2015-04-30

申请号：US14063070

申请日：2013-10-25

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer

IPC: G05B19/18

CPC classification number: G05B19/18 ,  G05B23/0221 ,  G08G1/0962 ,  G08G1/16

Abstract: A trace correlation system includes a data source, a controller, a probe component, and a tool. The data source is configured to provide raw data. The controller is configured to receive the raw data and generate trace information in response to the raw data. The probe component is configured to generate a data record from the raw data. The tool is configured to link the data record with the trace information.

Abstract translation: 跟踪相关系统包括数据源，控制器，探针组件和工具。 数据源被配置为提供原始数据。 控制器被配置为接收原始数据并响应原始数据生成跟踪信息。 探测组件被配置为从原始数据生成数据记录。 该工具被配置为将数据记录与跟踪信息相链接。

公开(公告)号：US20140189437A1

公开(公告)日：2014-07-03

申请号：US13762660

申请日：2013-02-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Albrecht Mayer

IPC: G06F11/34

CPC classification number: G06F11/3495 ,  G06F11/3024 ,  G06F11/3027 ,  G06F11/3068 ,  G06F11/3471 ,  G06F11/3476 ,  G06F11/364 ,  G06F2201/805

Abstract: The disclosure relates to methods and systems for trace solutions in a computer processing system. More specifically, the disclosure relates to methods and systems for a multi-tier trace architecture. A method for separating raw trace data includes receiving raw trace data from one of more CPUs and/or busses in the system, separating the raw trace data into high bandwidth trace information (HBTI) and low bandwidth trace information (LBTI), recording the HBTI on an on-chip trace buffer until a specific event is triggered, and providing in parallel the LBTI over an off-chip trace interface. In one embodiment, the raw trace data are provided to a separate HBTI trace unit and a separate LBTI respectively. The HBTI trace unit processes the HBTI and generates a HBTI message, and the LBTI trace unit processes the LBTI and generates a LBTI message.

Abstract translation: 本公开涉及计算机处理系统中的跟踪解决方案的方法和系统。 更具体地，本公开涉及用于多层跟踪架构的方法和系统。 用于分离原始迹线数据的方法包括从系统中的多个CPU和/或总线中的一个接收原始跟踪数据，将原始跟踪数据分离成高带宽跟踪信息（HBTI）和低带宽跟踪信息（LBTI），记录HBTI 在片内跟踪缓冲器上，直到触发特定事件，并且通过片外跟踪接口并行提供LBTI。 在一个实施例中，原始迹线数据分别提供给单独的HBTI跟踪单元和单独的LBTI。 HBTI跟踪单元处理HBTI并生成HBTI消息，LBTI跟踪单元处理LBTI并生成LBTI消息。

公开(公告)号：US12287862B2

公开(公告)日：2025-04-29

申请号：US17981583

申请日：2022-11-07

Applicant: Infineon Technologies AG

Inventor： Sandeep Vangipuram ,  Glenn Farrall ,  Albrecht Mayer ,  Frank Hellwig

IPC: G06F21/44 ,  G06F21/60 ,  G06F21/62 ,  G06F21/71 ,  G06F21/78

Abstract: A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.

公开(公告)号：US20230401341A1

公开(公告)日：2023-12-14

申请号：US17805984

申请日：2022-06-08

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Joerg Syassen ,  Glenn Ashley Farrall ,  Manfred Zimmerman

IPC: G06F21/78

CPC classification number: G06F21/78 ,  H04L9/3247

Abstract: A non-volatile memory (NVM) system external to a processor comprising an NVM and a memory controller may perform various aspects of the techniques. The NVM may store a first cryptographic signature and first data. The memory controller may, responsive to a first write request to write updated data to at least a portion of the NVM, to store the updated data in the NVM along with the first data to create second data. The memory controller may also generate, a second cryptographic signature that always differs from the first cryptographic signature, and store the second cryptographic signature as a current cryptographic signature. The memory controller may further output, to the processor, the current cryptographic signature as a reference signature, where the memory controller always replaces the current cryptographic signature, with cryptographic properties, whenever the NVM is written to and does not otherwise permit writing the current cryptographic signature.

公开(公告)号：US11562079B2

公开(公告)日：2023-01-24

申请号：US16662271

申请日：2019-10-24

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Reinhard Deml ,  Viola Rieger ,  Alexander Zeh

IPC: G06F21/00 ,  G06F21/60 ,  G06F21/62 ,  G06F21/53 ,  G06F15/78 ,  G06F11/27 ,  G06F11/22 ,  G06F12/14

Abstract: In different example embodiments, a system-on-chip is provided. The system-on-chip can have a control circuit with a plurality of control circuit areas, wherein the control circuit is configured to control a device, a security circuit which has a separately secured key memory and a hardware accelerator for cryptographic operations, wherein the security circuit is configured to electively enable either a read-only access or a read and write access to at least one of the control circuit areas, wherein the security circuit is furthermore configured to provide a communication path by means of the key memory and the hardware accelerator for the secured communication with a diagnostic system disposed outside the security circuit, to make the selection between the read access and the read and write access to the at least one selected area of the control circuit depending on a certificate supplied to the security circuit and authenticated by means of information stored in the key memory, and to execute the read access or the read and write access.

公开(公告)号：US20200150962A1

公开(公告)日：2020-05-14

申请号：US16678215

申请日：2019-11-08

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Neil Stuart Hastie ,  Pawel Jewstafjew

IPC: G06F9/30

Abstract: Handling an exception includes (i) executing a return from an exception; and (ii) executing a subsequent instruction with an additional functionality in case the additional functionality of the subsequent instruction can be triggered by a special instruction.

公开(公告)号：US20190026213A1

公开(公告)日：2019-01-24

申请号：US16037299

申请日：2018-07-17

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer

IPC: G06F11/36 ,  G06F9/38 ,  G06F9/30

Abstract: A method includes invoking a first instruction that, when executed by a first processor, causes the first processor to perform a first operation, and that, when executed by the first processor, causes a second processor to perform a second operation. The method further includes a second instruction that, when executed by the first processor, causes the first processor to perform the first operation while causing the second processor to perform a third operation or while leaving the second processor unaffected. A control system includes a first processor and a second processor, wherein the first processor is configured to execute a first instruction to perform a first operation, wherein the second processor is configured to perform a second operation when the first processor executes the first instruction.

公开(公告)号：US09699184B2

公开(公告)日：2017-07-04

申请号：US14483645

申请日：2014-09-11

Applicant: Infineon Technologies AG

Inventor： Laurent Heidt ,  Albrecht Mayer

IPC: H04L29/06

CPC classification number: H04L63/0876 ,  G06F2201/83 ,  H04L63/0823 ,  H04L63/123

Abstract: A method for processing data is suggested, and includes (i) conveying input data from a safety component to a security component, and (ii) calculating, at the security component, a second identifier based on the input data. The method further includes (iii) conveying the second identifier to the safety component, and (iv) verifying, at the safety component, a first identifier based on the second identifier.

公开(公告)号：US20150220755A1

公开(公告)日：2015-08-06

申请号：US14597860

申请日：2015-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Albrecht Mayer ,  Rafael Zalman

IPC: G06F21/62 ,  G06F13/42

CPC classification number: G06F21/6218 ,  G06F13/4221 ,  G06F21/606

Abstract: A method is disclosed for transmitting user data, wherein a first codeword is initially calculated using a transmit-side time value. The user data are then transmitted together with the first codeword to a receiver. The method continues with the calculation of a second codeword using a receive-side time value. If the first codeword and the calculated second codeword do not match one another, the user data are marked in the receiver.

Abstract translation: 公开了一种用于发送用户数据的方法，其中使用发送侧时间值最初计算第一码字。 然后将用户数据与第一码字一起发送到接收机。 该方法继续使用接收侧时间值计算第二码字。 如果第一码字和所计算的第二码字彼此不匹配，则在接收机中标记用户数据。

公开(公告)号：US20140095846A1

公开(公告)日：2014-04-03

申请号：US13632529

申请日：2012-10-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Albrecht Mayer

IPC: G06F9/30

CPC classification number: G06F11/3476

Abstract: A method for performing trace based measurement for a plurality of CPUs in parallel includes receiving a signal to perform a CPU parallel trace mode and enabling a parallel trace mode multiplexer to output all trace data, representing all data writes to the local memory, to a single observation unit. In one embodiment, the single observation unit is a processor observation block (POB), and in another embodiment, a bus observation block (BOB). If the single observation unit is a BOB, then the parallel trace mode multiplexer first routes the local memory data trace through a BOB adaptation layer to convert the CPU trace output data to data which is understood by the BOB.

Abstract translation: 用于并行地对多个CPU进行基于跟踪的测量的方法包括：接收信号以执行CPU并行跟踪模式，并使并行跟踪模式多路复用器将表示对本地存储器的所有数据写入的所有跟踪数据输出到单个 观察单位。 在一个实施例中，单个观察单元是处理器观察块（POB），在另一个实施例中是总线观察块（BOB）。 如果单个观察单元是BOB，则并行跟踪模式多路复用器首先通过BOB适配层路由本地存储器数据跟踪，以将CPU跟踪输出数据转换为由BOB理解的数据。