公开(公告)号：US20240145996A1

公开(公告)日：2024-05-02

申请号：US18395069

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS ,  James A. McCALL

IPC: H01R13/6471 ,  H01R12/73

CPC classification number: H01R13/6471 ,  H01R12/737

Abstract: A new connector implemented with connector pins to reduce crosstalk significantly improves memory channel electrical performance for next generation DDR (double data rate) technology. To reduce crosstalk the connector pins include pins with three different pin shapes, including two differently shaped signal pins and a ground pin that combines the shapes of the signal pins. The shaped pins enables them to be positioned in a connector so that each signal pin can have its own independent and separate signal return path on a single ground pin. In this manner, crosstalk can be significantly reduced.

公开(公告)号：US20230136268A1

公开(公告)日：2023-05-04

申请号：US18086634

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  John V. LOVELACE ,  George VERGIS

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes data buffer to memory chip write training circuitry. The data buffer to memory chip write training circuitry to send MDQ/MDQS phase relationship programming information, write commands and read commands to the data buffer chips for multiple write training iterations without a host memory controller having provided the MDQ/MDQS phase relationship programming information, the write commands and the read commands to the data buffer to memory chip write training circuitry.

公开(公告)号：US20230071117A1

公开(公告)日：2023-03-09

申请号：US17987687

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Hussein ALAMEER ,  Bill NALE ,  George VERGIS ,  Rajat AGARWAL

IPC: G06F3/06

Abstract: A memory module has a registering clock driver (RCD) that issues two column address strobe (CAS) commands with a single memory access command to exchange a double amount of data per dynamic random access memory (DRAM) device per memory access command. With double the amount of data per DRAM device, the memory module can provide double the pseudo channels as compared to a memory module where a single CAS command is issued per access command. The RCD can time division multiplex separate first commands for a first group of the DRAM devices from second commands for a second group of the DRAM devices on the command/address (CA) bus.

公开(公告)号：US20220391007A1

公开(公告)日：2022-12-08

申请号：US17886366

申请日：2022-08-11

Applicant: Intel Corporation

Inventor： Min Suet LIM ,  George VERGIS ,  Stephen P. CHRISTIANSON ,  Ankita TIWARI ,  Virendra Vikramsinh ADSURE

IPC: G06F1/3234 ,  H01L23/14

Abstract: Apparatus, assemblies, and platforms employing modular power voltage regulator (VR) modules to provide power to memory modules. A power VR module includes VR circuitry integrated on or coupled to a substrate with wiring coupling the VR circuitry to connector elements in first and second connector means. An assembly further includes a pair of memory modules (e.g., DDR) that are coupled to a power VR module via mating connector means. The connector means may be coupled using a Compression Mount Technology (CMT) connector disposed between arrays of CMT contact pads on the power VR module and the memory modules, or may comprise BGAs, PGAs, and LGAs. The power VR module receives one or more input voltages via one or both memory module and provide various output voltages to each of the memory modules to power memory devices and other circuitry on those modules.

公开(公告)号：US20220301608A1

公开(公告)日：2022-09-22

申请号：US17830118

申请日：2022-06-01

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  George VERGIS ,  John V. LOVELACE

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: An apparatus is described. The apparatus includes a register clock redriver (RCD) chip comprising a buffer communication (BCOM) interface, a BCOM training control circuit and BCOM training control register space, the BCOM training control circuit is to: transmit a series of symbol transmissions over the BCOM interface to a data buffer with different respective clock phase delays to sweep the symbol transmissions within an eye window; collect resultants of the symbol transmissions from the data buffer; and, perform an analysis on the resultants to determine an appropriate clock phase within the eye window.

公开(公告)号：US20220276958A1

公开(公告)日：2022-09-01

申请号：US17747950

申请日：2022-05-18

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  George VERGIS ,  Tonia M. ROSE ,  John R. GOLES ,  John V. LOVELACE

IPC: G06F12/06

Abstract: A memory chip is described. The memory chip includes self identification circuitry to self identify the memory chip. The self identification circuitry is to determine a resistance of a resistor and correlate the memory chip's identity to the resistance. A registering clock driver (RCD) chip is described. The RCD chip includes a controller. The controller is to receive provisional IDs (PIDs) from memory chips on a same memory module as the RCD chip. The controller is to program the memory chips with respective logical IDs (LIDs) based on a correlation of the PIDs and the LIDs.

公开(公告)号：US20220122929A1

公开(公告)日：2022-04-21

申请号：US17561892

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS ,  James A. McCALL

IPC: H01L23/66 ,  H01L23/552 ,  H01L23/00

Abstract: An integrated circuit package includes a substrate with traces for high speed communication that are subject to crosstalk. The traces include overlapping pads on different layers of the substrate, which can increase the mutual capacitance of the signal lines, which will offset the mutual inductance. Thus, the overlapping pads can reduce the crosstalk between the signal traces.

公开(公告)号：US20220012187A1

公开(公告)日：2022-01-13

申请号：US17484252

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Gustavo K. CONTRERAS MUNOZ ,  Raghunandan MAKARAM ,  George VERGIS

IPC: G06F12/14 ,  G06F21/64 ,  G06F13/42

Abstract: A cryptographic hash based on content of a Sideband Bus Device (SPD) Hub and serial number identifiers for components on a memory module is provided. The cryptographic hash provides the ability to mitigate various supply chain attacks by binding the SPD Hub content to a memory module certificate that is used for authentication. Based on the cryptographic signatures, a certificate is trusted by the platform so the binding of the SPD hub content to the memory module certificate creates a secure way to ensure the components on the memory module have not been tampered with and that the reported attributes of the memory module are correct.

公开(公告)号：US20210313743A1

公开(公告)日：2021-10-07

申请号：US17352211

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS

IPC: H01R13/633 ,  H01R13/635 ,  H01R12/73

Abstract: Apparatus
An apparatus is described. The apparatus includes a dual-in line memory module (DIMM) socket having a first latch and a second latch. One of the first latch and the second latch having a feature for a user to apply force to release a DIMM from the DIMM socket. The other of the first latch and the second latch not having a feature for the user to apply force so that one end of the DIMM releases before an opposite end of the DIMM during release of the DIMM from the DIMM socket.

公开(公告)号：US20210151083A1

公开(公告)日：2021-05-20

申请号：US17133484

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Aiswarya M. PIOUS ,  Raji JAMES ,  Phani K. ALAPARTHI ,  George VERGIS ,  Bill NALE ,  Konika GANGULY

IPC: G11C5/14

Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.