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    UNIFIED ENVIRONMENTAL MAPPING FRAMEWORK
    44.
    发明申请
    UNIFIED ENVIRONMENTAL MAPPING FRAMEWORK 审中-公开

    公开(公告)号：US20180342098A1

    公开(公告)日：2018-11-29

    申请号：US15778028

    申请日：2015-12-25

    Applicant: Intel Corporation

    Inventor： Yuanzhang Chang ,  Shaohui Jiao ,  Xiaofeng Tong ,  Qiang Li ,  Wenlong Li

    IPC: G06T15/50 ,  G06T15/04

    Abstract: Methods and apparatus relating to a unified environmental mapping framework are described. In an embodiment, Environmental Mapping (EM) logic performs one or more operations to extract illumination information for an object from an environmental map in response to a determination that the object has a diffuse surface and/or specular surface. Memory, coupled to the EM logic, stores data corresponding to the environmental map. Other embodiments are also disclosed and claimed.

    TECHNOLOGIES FOR REDUCED CONTROL AND STATUS REGISTER ACCESS LATENCY
    45.
    发明申请
    TECHNOLOGIES FOR REDUCED CONTROL AND STATUS REGISTER ACCESS LATENCY 审中-公开

    公开(公告)号：US20180095889A1

    公开(公告)日：2018-04-05

    申请号：US15283318

    申请日：2016-10-01

    Applicant: Intel Corporation

    Inventor： Xueyan Wang ,  Wenjuan Mao ,  Qiang Li ,  John V. Lovelace ,  James R. Goffena

    IPC: G06F12/0895 ,  G06F12/0875 ,  G06F12/10 ,  G06F9/445

    CPC classification number: G06F9/44505 ,  G06F12/0875 ,  G06F13/00 ,  G06F2212/452

    Abstract: Technologies for control and status register (CSR) access include a computing device that starts a firmware initialization phase. The firmware accesses a CSR at an abstract CSR address. The computing device determines whether an upper part of the CSR address matches a cached upper part of a previously accessed CSR address. If the upper parts do not match, the computing device converts the CSR address into a physical address and caches the upper part of the CSR address and the upper part of the physical address. If the upper parts match, the computing device combines a cached upper part of a previously accessed physical address with an offset of the CSR address. The upper part may include 20 bits and the lower part may include 12 bits. The physical address may be a PCIe address of the CSR added with an MMCFG base address. Other embodiments are described and claimed.

    CHIP MULTI-LAYER TRANSFORMER AND INDUCTOR
    48.
    发明公开
    CHIP MULTI-LAYER TRANSFORMER AND INDUCTOR 审中-公开

    公开(公告)号：US20240029942A1

    公开(公告)日：2024-01-25

    申请号：US18200062

    申请日：2023-05-22

    Applicant: Intel corporation

    Inventor： Chuanzhao Yu ,  Qiang Li ,  David Newman

    IPC: H01F27/28 ,  H01F41/04

    CPC classification number: H01F27/2804 ,  H01F41/041 ,  H01F2027/2809

    Abstract: A stacked transformer or inductor apparatus including a first layer with a first layer wire element extending around a center axis and a second layer with a second layer wire element. The second layer element includes side by side first and second wire sections in parallel spaced relation extending around the center axis and the first wire section is connected to the first layer wire element to form a primary turn winding. A third layer includes a third layer wire element extending around the center axis and connected to the second wire section of the second layer wire element to form a secondary turn winding partially overlapping with the primary turn winding.

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