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公开(公告)号：US20190385048A1
公开(公告)日：2019-12-19
申请号：US16012475
申请日：2018-06-19
发明人： Andrew S. Cassidy , Rathinakumar Appuswamy , John V. Arthur , Pallab Datta , Steven K. Esser , Myron D. Flickner , Jennifer Klamo , Dharmendra S. Modha , Hartmut Penner , Jun Sawada , Brian Taba
摘要： Hardware neural network processors, are provided. A neural core includes a weight memory, an activation memory, a vector-matrix multiplier, and a vector processor. The vector-matrix multiplier is adapted to receive a weight matrix from the weight memory, receive an activation vector from the activation memory, and compute a vector-matrix multiplication of the weight matrix and the activation vector. The vector processor is adapted to receive one or more input vector from one or more vector source and perform one or more vector functions on the one or more input vector to yield an output vector. In some embodiments a programmable controller is adapted to configure and operate the neural core.
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42.发明申请公开(公告)号：US20190385046A1
公开(公告)日：2019-12-19
申请号：US16008949
申请日：2018-06-14
发明人： Andrew S. Cassidy , Myron D. Flickner , Pallab Datta , Hartmut Penner , Rathinakumar Appuswamy , Jun Sawada , John V. Arthur , Dharmendra S. Modha , Steven K. Esser , Brian Taba , Jennifer Klamo
摘要： Neural network processing hardware using parallel computational architectures with reconfigurable core-level and vector-level parallelism is provided. In various embodiments, a neural network model memory is adapted to store a neural network model comprising a plurality of layers. Each layer has at least one dimension and comprises a plurality of synaptic weights. A plurality of neural cores is provided. Each neural core includes a computation unit and an activation memory. The computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The computation unit has a plurality of vector units. The activation memory is adapted to store the input activations and the output activations. The system is adapted to partition the plurality of cores into a plurality of partitions based on dimensions of the layer and the vector units.
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43.发明申请公开(公告)号：US20190303740A1
公开(公告)日：2019-10-03
申请号：US15941985
申请日：2018-03-30
摘要： Block transfer of neuron output values through data memory for neurosynaptic processors is provided, which in some embodiments includes time-multiplexing. A neurosynaptic core is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. Synaptic weights for one of a plurality of logical cores are read. The neurosynaptic core is configured to implement the one of the plurality of logical cores using the synaptic weights. At least one data block is provided as contiguous input activations to the neurosynaptic core. The input activations are processed by the neurosynaptic core to determine at least one contiguous block of output activations.
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公开(公告)号：US20190278320A1
公开(公告)日：2019-09-12
申请号：US16423928
申请日：2019-05-28
发明人： Arnon Amir , Pallab Datta , Dharmendra S. Modha
摘要： Reduction in the number of neurons and axons in a neurosynaptic network while maintaining its functionality is provided. A neural network description describing a neural network is read. One or more functional unit of the neural network is identified. The one or more functional unit of the neural network is optimized. An optimized neural network description is written based on the optimized functional unit.
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公开(公告)号：US10204301B2
公开(公告)日：2019-02-12
申请号：US14662096
申请日：2015-03-18
发明人： Arnon Amir , Rathinakumar Appuswamy , Pallab Datta , Myron D. Flickner , Paul A. Merolla , Dharmendra S. Modha , Benjamin G. Shaw
摘要： One embodiment of the invention provides a system for mapping a neural network onto a neurosynaptic substrate. The system comprises a reordering unit for reordering at least one dimension of an adjacency matrix representation of the neural network. The system further comprises a mapping unit for selecting a mapping method suitable for mapping at least one portion of the matrix representation onto the substrate, and mapping the at least one portion of the matrix representation onto the substrate utilizing the mapping method selected. The system further comprises a refinement unit for receiving user input regarding at least one criterion relating to accuracy or resource utilization of the substrate. The system further comprises an evaluating unit for evaluating each mapped portion against each criterion. Each mapped portion that fails to satisfy a criterion may be remapped to allow trades offs between accuracy and resource utilization of the substrate.
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公开(公告)号：US10140551B2
公开(公告)日：2018-11-27
申请号：US15993482
申请日：2018-05-30
发明人： Alexander Andreopoulos , Rathinakumar Appuswamy , Pallab Datta , Steven K. Esser , Dharmendra S. Modha
IPC分类号： G06K9/62 , G06K9/52 , G06K9/46 , H04N19/136 , G06N3/063 , H04N9/67 , G06K9/00 , G06K9/66 , G06N3/08 , G06T7/246
摘要： Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.
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公开(公告)号：US20180276502A1
公开(公告)日：2018-09-27
申请号：US15993482
申请日：2018-05-30
发明人： Alexander Andreopoulos , Rathinakumar Appuswamy , Pallab Datta , Steven K. Esser , Dharmendra S. Modha
IPC分类号： G06K9/62 , H04N9/67 , G06K9/46 , G06T7/246 , G06N3/08 , G06N3/063 , G06K9/66 , G06K9/52 , H04N19/136 , G06K9/00
CPC分类号： G06K9/6256 , G06K9/00718 , G06K9/00986 , G06K9/46 , G06K9/4623 , G06K9/4652 , G06K9/4661 , G06K9/4671 , G06K9/4676 , G06K9/52 , G06K9/6267 , G06K9/66 , G06N3/0635 , G06N3/08 , G06T7/246 , G06T2207/10016 , G06T2207/20081 , H04N9/67 , H04N19/136
摘要： Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.
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公开(公告)号：US09704094B2
公开(公告)日：2017-07-11
申请号：US14626677
申请日：2015-02-19
发明人： Arnon Amir , David J. Berg , Pallab Datta , Myron D. Flickner , Paul A. Merolla , Dharmendra S. Modha , Benjamin G. Shaw , Brian S. Taba
摘要： One embodiment of the invention provides a method comprising defining a brainlet representing a platform-agnostic network of neurons, synapses, and axons. The method further comprises compiling the brainlet into a corelet for mapping onto neurosynaptic substrate, and mapping the corelet onto the neurosynaptic substrate. The corelet is compatible with one or more conditions related to the neurosynaptic substrate.
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公开(公告)号：US20160247062A1
公开(公告)日：2016-08-25
申请号：US14626677
申请日：2015-02-19
发明人： Arnon Amir , David J. Berg , Pallab Datta , Myron D. Flickner , Paul A. Merolla , Dharmendra S. Modha , Benjamin G. Shaw , Brian S. Taba
摘要： One embodiment of the invention provides a method comprising defining a brainlet representing a platform-agnostic network of neurons, synapses, and axons. The method further comprises compiling the brainlet into a corelet for mapping onto neurosynaptic substrate, and mapping the corelet onto the neurosynaptic substrate. The corelet is compatible with one or more conditions related to the neurosynaptic substrate.
摘要翻译： 本发明的一个实施例提供了一种方法，包括定义表示神经元，突触和轴突的平台不可知网络的脑部。 该方法还包括将该脑片编成一个芯片，以映射到神经突触底物上，并将该芯片映射到神经突触底物上。 骨架与一种或多种与神经突触底物相关的病症相容。
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公开(公告)号：US09424284B2
公开(公告)日：2016-08-23
申请号：US14690326
申请日：2015-04-17
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Pallab Datta , Paul A. Merolla , Dharmendra S. Modha
摘要： Embodiments of the invention relate to mapping neural dynamics of a neural model on to a lookup table. One embodiment comprises defining a phase plane for a neural model. The phase plane represents neural dynamics of the neural model. The phase plane is coarsely sampled to obtain state transition information for multiple neuronal states. The state transition information is mapped on to a lookup table.
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