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公开(公告)号：US20220121951A1
公开(公告)日：2022-04-21
申请号：US17076287
申请日：2020-10-21
发明人： Andrew Stephen Cassidy , Rathinakumar Appuswamy , John Vernon Arthur , Jun Sawada , Dharmendra S. Modha , Michael Vincent DeBole , Pallab Datta , Tapan Kumar Nayak
摘要： Conflict-free, stall-free, broadcast networks on neural inference chips are provided. In various embodiments, a neural inference chip comprises a plurality of network nodes and a network on chip interconnecting the plurality of network nodes. The network comprises at least one pair of directional paths. The paths of each pair have opposite directions and a common end. The network is configured to accept data at any of the plurality of nodes. The network is configured to propagate data along a first of the pair of directional paths from a source node to the common end of the pair of directional paths and along a second of the pair of directional paths from the common end of the pair of directional paths to one or more destination node.
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公开(公告)号：US11263011B2
公开(公告)日：2022-03-01
申请号：US16202871
申请日：2018-11-28
发明人： Andrew S. Cassidy , Rathinakumar Appuswamy , John V. Arthur , Pallab Datta , Michael V. Debole , Steven K. Esser , Myron D. Flickner , Dharmendra S. Modha , Hartmut Penner , Jun Sawada , Brian Taba
摘要： A device for controlling neural inference processor cores is provided, including a compound instruction set architecture. The device comprises an instruction memory, which comprises a plurality of instructions for controlling a neural inference processor core. Each of the plurality of instructions comprises a control operation. The device further comprises a program counter. The device further comprises at least one loop counter register. The device is adapted to execute the plurality of instructions. Executing the plurality of instructions comprises: reading an instruction from the instruction memory based on a value of the program counter; updating the at least one loop counter register according to the control operation of the instruction; and updating the program counter according to the control operation of the instruction and a value of the at least one loop counter register.
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公开(公告)号：US10755166B2
公开(公告)日：2020-08-25
申请号：US15184908
申请日：2016-06-16
摘要： Embodiments of the present invention provide a method for feature extraction using multiple neurosynaptic core circuits including one or more input core circuits for receiving input and one or more output core circuits for generating output. The method comprises receiving a set of input data via the input core circuits, and extracting a first set of features from the input data using the input core circuits. Each feature of the first set of features is based on a subset of the input data. The method further comprises reordering the first set of features using the input core circuits, and generating a second set of features by combining the reordered first set of features using the output core circuits. The second set of features comprises a set of features with reduced correlation. Each feature of the second set of features is based on the entirety of said set of input data.
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公开(公告)号：US10558892B2
公开(公告)日：2020-02-11
申请号：US16147106
申请日：2018-09-28
发明人： Alexander Andreopoulos , Rathinakumar Appuswamy , Pallab Datta , Steven K. Esser , Dharmendra S. Modha
IPC分类号： G06K9/62 , G06K9/46 , H04N19/136 , G06K9/52 , G06K9/66 , G06N3/063 , G06N3/08 , G06T7/246 , G06K9/00 , H04N9/67
摘要： Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.
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公开(公告)号：US20190385048A1
公开(公告)日：2019-12-19
申请号：US16012475
申请日：2018-06-19
发明人： Andrew S. Cassidy , Rathinakumar Appuswamy , John V. Arthur , Pallab Datta , Steven K. Esser , Myron D. Flickner , Jennifer Klamo , Dharmendra S. Modha , Hartmut Penner , Jun Sawada , Brian Taba
摘要： Hardware neural network processors, are provided. A neural core includes a weight memory, an activation memory, a vector-matrix multiplier, and a vector processor. The vector-matrix multiplier is adapted to receive a weight matrix from the weight memory, receive an activation vector from the activation memory, and compute a vector-matrix multiplication of the weight matrix and the activation vector. The vector processor is adapted to receive one or more input vector from one or more vector source and perform one or more vector functions on the one or more input vector to yield an output vector. In some embodiments a programmable controller is adapted to configure and operate the neural core.
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46.发明申请公开(公告)号：US20190385046A1
公开(公告)日：2019-12-19
申请号：US16008949
申请日：2018-06-14
发明人： Andrew S. Cassidy , Myron D. Flickner , Pallab Datta , Hartmut Penner , Rathinakumar Appuswamy , Jun Sawada , John V. Arthur , Dharmendra S. Modha , Steven K. Esser , Brian Taba , Jennifer Klamo
摘要： Neural network processing hardware using parallel computational architectures with reconfigurable core-level and vector-level parallelism is provided. In various embodiments, a neural network model memory is adapted to store a neural network model comprising a plurality of layers. Each layer has at least one dimension and comprises a plurality of synaptic weights. A plurality of neural cores is provided. Each neural core includes a computation unit and an activation memory. The computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The computation unit has a plurality of vector units. The activation memory is adapted to store the input activations and the output activations. The system is adapted to partition the plurality of cores into a plurality of partitions based on dimensions of the layer and the vector units.
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公开(公告)号：US10204301B2
公开(公告)日：2019-02-12
申请号：US14662096
申请日：2015-03-18
发明人： Arnon Amir , Rathinakumar Appuswamy , Pallab Datta , Myron D. Flickner , Paul A. Merolla , Dharmendra S. Modha , Benjamin G. Shaw
摘要： One embodiment of the invention provides a system for mapping a neural network onto a neurosynaptic substrate. The system comprises a reordering unit for reordering at least one dimension of an adjacency matrix representation of the neural network. The system further comprises a mapping unit for selecting a mapping method suitable for mapping at least one portion of the matrix representation onto the substrate, and mapping the at least one portion of the matrix representation onto the substrate utilizing the mapping method selected. The system further comprises a refinement unit for receiving user input regarding at least one criterion relating to accuracy or resource utilization of the substrate. The system further comprises an evaluating unit for evaluating each mapped portion against each criterion. Each mapped portion that fails to satisfy a criterion may be remapped to allow trades offs between accuracy and resource utilization of the substrate.
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公开(公告)号：US10140551B2
公开(公告)日：2018-11-27
申请号：US15993482
申请日：2018-05-30
发明人： Alexander Andreopoulos , Rathinakumar Appuswamy , Pallab Datta , Steven K. Esser , Dharmendra S. Modha
IPC分类号： G06K9/62 , G06K9/52 , G06K9/46 , H04N19/136 , G06N3/063 , H04N9/67 , G06K9/00 , G06K9/66 , G06N3/08 , G06T7/246
摘要： Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.
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公开(公告)号：US10115054B2
公开(公告)日：2018-10-30
申请号：US14322778
申请日：2014-07-02
摘要： Embodiments of the invention provide a method comprising receiving a set of features extracted from input data, training a linear classifier based on the set of features extracted, and generating a first matrix using the linear classifier. The first matrix includes multiple dimensions. Each dimension includes multiple elements. Elements of a first dimension correspond to the set of features extracted. Elements of a second dimension correspond to a set of classification labels. The elements of the second dimension are arranged based on one or more synaptic weight arrangements. Each synaptic weight arrangement represents effective synaptic strengths for a classification label of the set of classification labels. The neurosynaptic core circuit is programmed with synaptic connectivity information based on the synaptic weight arrangements. The core circuit is configured to classify one or more objects of interest in the input data.
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公开(公告)号：US20180276502A1
公开(公告)日：2018-09-27
申请号：US15993482
申请日：2018-05-30
发明人： Alexander Andreopoulos , Rathinakumar Appuswamy , Pallab Datta , Steven K. Esser , Dharmendra S. Modha
IPC分类号： G06K9/62 , H04N9/67 , G06K9/46 , G06T7/246 , G06N3/08 , G06N3/063 , G06K9/66 , G06K9/52 , H04N19/136 , G06K9/00
CPC分类号： G06K9/6256 , G06K9/00718 , G06K9/00986 , G06K9/46 , G06K9/4623 , G06K9/4652 , G06K9/4661 , G06K9/4671 , G06K9/4676 , G06K9/52 , G06K9/6267 , G06K9/66 , G06N3/0635 , G06N3/08 , G06T7/246 , G06T2207/10016 , G06T2207/20081 , H04N9/67 , H04N19/136
摘要： Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.
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