公开(公告)号：US20130227252A1

公开(公告)日：2013-08-29

申请号：US13802540

申请日：2013-03-13

申请人： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

发明人： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30094

摘要： A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first, second, and third source operands may be stored as a result of the add instruction. The sum may be stored partly in a destination operand indicated by the add instruction and partly a plurality of flags. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

摘要翻译： 一方面的方法可以包括接收添加指令。 加法指令可以指示第一源操作数，第二源操作数和第三源操作数。 作为加法指令的结果，可以存储第一，第二和第三源操作数的总和。 该和可以部分地存储在由加法指令指示的目的地操作数中，部分地存储在多个标志中。 还公开了其它方法，以及机器可读介质上的装置，系统和指令。

公开(公告)号：US08447962B2

公开(公告)日：2013-05-21

申请号：US12644440

申请日：2009-12-22

申请人： Christopher J. Hughes ,  Yen-Kuang (Y. K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

发明人： Christopher J. Hughes ,  Yen-Kuang (Y. K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3865

摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

摘要翻译： 根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

公开(公告)号：US20110161635A1

公开(公告)日：2011-06-30

申请号：US12655213

申请日：2009-12-26

申请人： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

发明人： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC分类号： G06F9/315

CPC分类号： G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

摘要： A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

摘要翻译： 一个方面的方法可以包括接收旋转指令。 旋转指令可以指示源操作数和旋转量。 结果可以存储在由旋转指令指示的目标操作数中。 结果可能使源操作数旋转了旋转量。 旋转指令的执行可以在不读取进位标志的情况下完成。

公开(公告)号：US20110153994A1

公开(公告)日：2011-06-23

申请号：US12645383

申请日：2009-12-22

申请人： Vinodh Gopal ,  James D. Guilford ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Gilbert M. Wolrich ,  Martin G. Dixon ,  Mark C. Davis ,  Sean P. Mirkes ,  Alexandre Farcy ,  Bret L. Toll ,  Maxim Loktyukhin

发明人： Vinodh Gopal ,  James D. Guilford ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Gilbert M. Wolrich ,  Martin G. Dixon ,  Mark C. Davis ,  Sean P. Mirkes ,  Alexandre Farcy ,  Bret L. Toll ,  Maxim Loktyukhin

IPC分类号： G06F9/302

CPC分类号： G06F9/30094 ,  G06F9/30014

摘要： A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

摘要翻译： 一方面的方法可以包括接收乘法指令。 乘法指令可以指示第一源操作数和第二源操作数。 第一和第二源操作数的乘积可以存储在由乘法指令指示的一个或多个目的地操作数中。 乘法指令的执行可以在不写进位标志的情况下完成。 还公开了其它方法，以及机器可读介质上的装置，系统和指令。

公开(公告)号：US07941651B1

公开(公告)日：2011-05-10

申请号：US10185876

申请日：2002-06-27

申请人： Bret L. Toll ,  John Alan Miller ,  Michael A. Fetterman

发明人： Bret L. Toll ,  John Alan Miller ,  Michael A. Fetterman

IPC分类号： G06F9/34

CPC分类号： G06F9/3001 ,  G06F9/30003 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017

摘要： A method and apparatus for combining micro-operations to process immediate data. The immediate data may be wider than the immediate data storage capacity of a micro-operation. A first micro-operation is issued to process a first portion of the immediate data, which can be processed within the immediate data storage capacity of a micro-operation. A second micro-operation is issued to process a second portion of the immediate data, which can be processed within the immediate data storage capacity of a micro-operation. Execution of the first and second micro-operations and optionally of a third micro-operation serves to reconstruct the immediate data comprising the first portion and the second portion of the immediate data.

摘要翻译： 一种用于组合微操作以处理即时数据的方法和装置。 即时数据可能比微操作的即时数据存储容量更宽。 发出第一微操作以处理即时数据的第一部分，其可以在微操作的即时数据存储容量内处理。 发出第二微操作以处理立即数据的第二部分，其可以在微操作的即时数据存储容量内处理。 执行第一和第二微操作以及可选地第三微操作用于重构包括即时数据的第一部分和第二部分的即时数据。

公开(公告)号：US06308279B1

公开(公告)日：2001-10-23

申请号：US09083281

申请日：1998-05-22

申请人： Bret L. Toll ,  Alan B. Kyker ,  Stephen H. Gunther

发明人： Bret L. Toll ,  Alan B. Kyker ,  Stephen H. Gunther

IPC分类号： G06F126

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/329 ,  Y02D10/128 ,  Y02D10/24 ,  Y02D50/20

摘要： A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.

摘要翻译： 一种用于多线程处理器中功率模式转换的方法和装置。 发布第一指示，包括与处理器中的第一逻辑处理器相关联的第一标识符，第一逻辑处理器已经进入功率模式。 发出第二指示，包括与处理器中的第二逻辑处理器相关联的第二标识符，第二逻辑处理器已经进入电源模式。 指示可以是例如停止授权确认特殊总线周期，指示逻辑处理器已经进入停止许可模式。 当第一和第二指示都已被发出时，处理器可以转换到睡眠模式。

公开(公告)号：US09658850B2

公开(公告)日：2017-05-23

申请号：US13976993

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30029 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

公开(公告)号：US09619236B2

公开(公告)日：2017-04-11

申请号：US13976992

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3802

摘要： An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

公开(公告)号：US20150032998A1

公开(公告)日：2015-01-29

申请号：US13997243

申请日：2012-02-02

申请人： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Alexandre J. Farcy ,  Bret L. Toll ,  Robert S. Chappell ,  Matthew C. Merten ,  Rajesh S. Parthasarathy ,  Per Hammarlund

发明人： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Alexandre J. Farcy ,  Bret L. Toll ,  Robert S. Chappell ,  Matthew C. Merten ,  Rajesh S. Parthasarathy ,  Per Hammarlund

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3859

摘要： An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similarly provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA.

摘要翻译： 这里描述了一种用于提供猜测控制指令的装置和方法。 提供xAcquire和xRelease指令来定义关键部分。 在一个实施例中，xAcquire指令包括具有检验前缀的锁定指令，并且xRelease指令包括具有检验前缀的锁定释放指令。 因此，处理器能够通过xAcquire和xRelease来删除锁定和事务性地执行在软件中定义的关键部分。 但是通过仅添加前缀提示，传统处理器能够通过忽略提示并执行传统的锁定关键部分来保证互斥，从而执行相同的代码。 此外，xBegin和xEnd在指令集架构（ISA）中类似地提供以定义事务代码区域。 此外，还在ISA中提供了其他控制推测指令，例如xAbort，以实现关键或事务代码段的显示中止，以及xTest测试推测执行状态。

公开(公告)号：US20140372727A1

公开(公告)日：2014-12-18

申请号：US13977734

申请日：2011-12-23

申请人： Robert Valentine ,  Bret L. Toll ,  Jesus Corbal ,  Jeff G. Wiedemeier ,  Sridhar Samudrala

发明人： Robert Valentine ,  Bret L. Toll ,  Jesus Corbal ,  Jeff G. Wiedemeier ,  Sridhar Samudrala

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3887

摘要： Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.

摘要翻译： 提供向量混合和置换功能，响应于指令：包括存储向量元素的字段的目的地向量寄存器，第一向量寄存器，向量元素大小，第二向量寄存器和第三操作数。 指数从第二个寄存器中的字段读取。 每个索引具有第一选择器部分和第二选择器部分。 对应的未屏蔽向量元素被存储到目的地寄存器的字段，其中响应于具有第一值的相应第一选择器部分的每个向量元素从第一寄存器的对应数据字段被复制到中间向量，并且响应于 具有第二值的相应的第一选择器部分从第三操作数的相应数据字段复制到中间向量。 然后，由对应的第二选择器部分索引的中间向量中的数据字段替换目的地的未屏蔽的数据字段。