公开(公告)号：US09964824B2

公开(公告)日：2018-05-08

申请号：US14793106

申请日：2015-07-07

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Arichika Ishida ,  Norihiro Uemura ,  Hidekazu Miyake ,  Hiroto Miyake ,  Yohei Yamaguchi

IPC: G09G3/36 ,  G02F1/1368 ,  G02F1/1333 ,  G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/136227 ,  H01L27/1288

Abstract: According to one embodiment, a display device includes a TFT on an insulating substrate. The TFT includes a gate electrode, an insulating layer on the gate electrode, a semiconductor layer on the insulating layer, and a source electrode and a drain electrode each provided in contact with at least a part of the semiconductor layer. The source and drain electrodes have a laminated structure including a lower layer, an intermediate layer and an upper layer. The source and drain electrodes include sidewalls each including a first tapered portion on the upper layer side, a second tapered portion on the lower layer side and a sidewall protective film attached to the second tapered portion. The taper angle of the first tapered portion is smaller than that of the second tapered portion.

公开(公告)号：US09391213B2

公开(公告)日：2016-07-12

申请号：US14245102

申请日：2014-04-04

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Norihiro Uemura ,  Takeshi Noda ,  Hidekazu Miyake ,  Yohei Yamaguchi

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78696 ,  G02F1/133345 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/1337 ,  G02F1/134309 ,  G02F1/1368 ,  G02F2001/133357 ,  H01L27/1225 ,  H01L27/1285 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78693

Abstract: In a bottom gate thin film transistor using a first oxide semiconductor layer as a channel layer, the first oxide semiconductor layer and second semiconductor layers include In and O. An (O/In) ratio of the second oxide semiconductor layers is equal to or larger than that of the first oxide semiconductor layer, and a film thickness thereof is thicker than that of the first oxide semiconductor layer.

Abstract translation: 在使用第一氧化物半导体层作为沟道层的底栅极薄膜晶体管中，第一氧化物半导体层和第二半导体层包括In和O.第二氧化物半导体层的（O / In）比等于或大于 比第一氧化物半导体层的厚度厚，其厚度比第一氧化物半导体层厚。

公开(公告)号：US09209306B2

公开(公告)日：2015-12-08

申请号：US13851162

申请日：2013-03-27

Applicant: Japan Display Inc.

Inventor： Norihiro Uemura ,  Takeshi Noda ,  Hidekazu Miyake ,  Isao Suzumura

IPC: G02F1/136 ,  H01L29/786 ,  G02F1/1368

CPC classification number: H01L29/78606 ,  G02F1/133602 ,  G02F1/1368 ,  H01L27/1225 ,  H01L29/7869

Abstract: A thin film transistor includes, an insulating substrate, a gate electrode provided on an upper surface of the insulating substrate, a gate insulating film formed so as to cover the gate electrode, an oxide semiconductor layer provided on the gate insulating film, a channel protective layer provided at least on an upper surface of the oxide semiconductor layer, and a source electrode and a drain electrode provided so as to come into contact with the oxide semiconductor layer, wherein the channel protective layer is formed such that the film density of a portion provided so as to come into contact with the oxide semiconductor layer is higher than the film density of a portion distant from the oxide semiconductor layer.

Abstract translation: 薄膜晶体管包括：绝缘基板，设置在绝缘基板的上表面上的栅电极，形成为覆盖栅电极的栅极绝缘膜，设置在栅极绝缘膜上的氧化物半导体层，沟道保护 至少设置在所述氧化物半导体层的上表面上的所述第一层和设置成与所述氧化物半导体层接触的源电极和漏电极，其中所述沟道保护层形成为使得所述沟道保护层的膜密度 设置成与氧化物半导体层接触的位置高于远离氧化物半导体层的部分的膜密度。