公开(公告)号：US20120156842A1

公开(公告)日：2012-06-21

申请号：US12979025

申请日：2010-12-27

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L21/336

CPC classification number: H01L27/11558 ,  G11C16/0441 ,  G11C2216/10

Abstract: A semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first conductive type well and a second conductive type well disposed on and/or over a semiconductor substrate; a first gate and a second gate disposed on and/or over the first conductive type well and the second conductive type well, respectively; a second conductive type first ion implantation region disposed in the first conductive type well at one side of the first gate and a second conductive type second ion implantation region disposed in the first conductive type well at the other side of the first gate; a first conductive type first ion implantation region disposed in the second conductive type well at one side of the second gate and a first conductive type second ion implantation region disposed in the second conductive type well at the other side of the second gate; and a line electrically connecting the second conductive type second ion implantation region with the first conductive type first ion implantation region.

Abstract translation: 半导体存储器件及其制造方法。 半导体存储器件包括第一导电型阱和布置在半导体衬底上和/或之上的第二导电类型阱; 分别设置在第一导电类型阱和第二导电类型阱上和/或上方的第一栅极和第二栅极; 设置在第一栅极一侧的第一导电类型阱中的第二导电型第一离子注入区和设置在第一栅极另一侧的第一导电类型阱中的第二导电型第二离子注入区; 设置在第二栅极一侧的第二导电类型阱中的第一导电型第一离子注入区和设置在第二栅极另一侧的第二导电类型阱中的第一导电型第二离子注入区; 以及将第二导电型第二离子注入区与第一导电型第一离子注入区电连接的线。

公开(公告)号：US20110140186A1

公开(公告)日：2011-06-16

申请号：US12965261

申请日：2010-12-10

Applicant: Dong Hoon Park ,  Jin Hyo Jung ,  Min Kyung Ko

Inventor： Dong Hoon Park ,  Jin Hyo Jung ,  Min Kyung Ko

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L29/66181 ,  H01L27/1085 ,  H01L27/10894 ,  H01L29/945

Abstract: Disclosed are a capacitor for a semiconductor device and a manufacturing method thereof. The capacitor includes a second oxide layer filling a first trench in a semiconductor substrate; second and third trenches in an active region at opposing sides of the second oxide layer in the first trench; a third oxide layer on the semiconductor substrate and on inner surfaces of the second and third trenches; and a polysilicon layer on the third oxide layer to fill the second and third trenches.

Abstract translation: 公开了一种用于半导体器件的电容器及其制造方法。 电容器包括填充半导体衬底中的第一沟槽的第二氧化物层; 在所述第一沟槽中的所述第二氧化物层的相对侧的有源区中的第二和第三沟槽; 半导体衬底上的第三氧化物层和第二和第三沟槽的内表面上的第三氧化物层; 以及在所述第三氧化物层上的多晶硅层以填充所述第二和第三沟槽。

公开(公告)号：US20100029051A1

公开(公告)日：2010-02-04

申请号：US12576714

申请日：2009-10-09

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/7885 ,  H01L29/7887

Abstract: Semiconductor devices and a fabricating method therefore are disclosed. One method includes forming a buffer oxide layer and a buffer nitride layer on the top surface of a semiconductor substrate; forming a photoresist pattern on the pad nitride layer and forming a trench by etching the buffer nitride layer, the buffer oxide layer and the semiconductor substrate by a predetermined etch using the photoresist pattern as a mask; forming sidewall floating gates on the lateral faces of the trench; depositing polysilicon on the entire surface of the resulting structure; forming a gate electrode by patterning the polysilicon of the resulting structure; removing the buffer nitride layer and forming a poly oxide layer on the exposed part of the polysilicon of the gate electrode; forming source/drain regions by implanting impurities into the predetermined part of the resulting structure; injecting electric charges into the sidewall floating gates; and forming spacers on the lateral faces of the sidewall floating gates and the gate electrode.

Abstract translation: 因此公开了半导体器件和制造方法。 一种方法包括在半导体衬底的顶表面上形成缓冲氧化物层和缓冲氮化物层; 通过使用光致抗蚀剂图案作为掩模通过预定蚀刻蚀刻缓冲氮化物层，缓冲氧化物层和半导体衬底，在衬垫氮化物层上形成光致抗蚀剂图案并形成沟槽; 在沟槽的侧面上形成侧壁浮动栅极; 在所得结构的整个表面上沉积多晶硅; 通过对所得结构的多晶硅进行构图来形成栅电极; 去除所述缓冲氮化物层并在所述栅电极的所述多晶硅的暴露部分上形成多晶氧化物层; 通过将杂质注入到所得结构的预定部分中来形成源极/漏极区域; 将电荷注入侧壁浮动门; 以及在侧壁浮动栅极和栅极电极的侧面上形成间隔物。

公开(公告)号：US20090321823A1

公开(公告)日：2009-12-31

申请号：US12556863

申请日：2009-09-10

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L29/78

CPC classification number: H01L29/665 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823468

Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided. The high voltage semiconductor device comprises: second conductive type drift regions disposed spaced from each other on a first conductive type well region formed on a first conductive type semiconductor substrate; a gate electrode on a channel region between the second conductive type drift regions with a gate insulating film disposed therebetween; second conductive type high-concentration source and drain each disposed in the second conductive type drift regions, spaced from a side of a gate electrode; a gate spacer having a spacer part covering the side of the gate electrode and a spacer extending part to cover a spaced portion of the second conductive type high-concentration source and drain from the side of the gate electrode; and a silicide formed on the gate electrode and the second conductive type high-concentration source and drain.

Abstract translation: 提供了高压半导体器件及其制造方法。 所述高电压半导体器件包括：在形成于第一导电类型半导体衬底上的第一导电类型阱区上彼此间隔设置的第二导电型漂移区; 位于第二导电型漂移区之间的沟道区上的栅电极，栅极绝缘膜位于它们之间; 第二导电型高浓度源极和漏极，每个设置在第二导电类型漂移区域中，与栅电极的一侧间隔开; 栅极间隔物，其具有覆盖所述栅电极侧的隔离物部分和间隔物延伸部分，以覆盖所述第二导电型高浓度源的间隔部分和从所述栅电极的侧面排出; 以及形成在栅电极和第二导电型高浓度源极和漏极上的硅化物。

公开(公告)号：US07544582B2

公开(公告)日：2009-06-09

申请号：US11205540

申请日：2005-08-16

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L21/76

CPC classification number: H01L21/823878 ,  H01L21/76229 ,  H01L21/76237

Abstract: A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate, dividing the semiconductor substrate into an active region and a field region; and a field channel stop ion implantation layer in the semiconductor substrate under the STI layer.

Abstract translation: 半导体器件及其制造方法可以提高隔离特性，而不会降低结二极管特性和增加MOS晶体管的阈值电压。 该器件包括半导体衬底; 在所述半导体衬底的预定部分中的STI层，将所述半导体衬底分成有源区和场区; 以及在STI层下的半导体衬底中的场通道停止离子注入层。

公开(公告)号：US07538378B2

公开(公告)日：2009-05-26

申请号：US11022889

申请日：2004-12-28

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L29/94

CPC classification number: H01L29/42324 ,  G11C16/0425 ,  G11C16/10 ,  H01L21/28273

Abstract: A flash memory device and programming and erasing methods therewith is disclosed, to secure the programming and erasing characteristics by changing a structure of a floating gate, in which the flash memory device includes a first conductive type semiconductor substrate defined as a field area and an active area; a tunnel oxide layer on the active area of the first conductive type semiconductor substrate; a floating gate on the tunnel oxide layer, having at least first and second floating gates having different levels of energy band gap; a dielectric layer on the floating gate; a control gate on the dielectric layer; and second conductive type source/drain regions in the active area of the first conductive type semiconductor substrate at both sides of the floating gate.

Abstract translation: 公开了一种闪存器件及其编程和擦除方法，以通过改变浮动栅极的结构来确保编程和擦除特性，其中闪存器件包括被定义为场区域的第一导电类型半导体衬底和有源 区; 在所述第一导电型半导体衬底的有源区上的隧道氧化物层; 隧道氧化物层上的浮置栅极，具有至少具有不同能级能隙的第一和第二浮栅; 浮栅上的电介质层; 电介质层上的控制栅极; 以及在浮置栅极两侧的第一导电型半导体衬底的有源区域中的第二导电型源极/漏极区域。

公开(公告)号：US07521311B2

公开(公告)日：2009-04-21

申请号：US11129002

申请日：2005-05-13

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L21/336

CPC classification number: H01L29/66484 ,  H01L21/28052 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7831

Abstract: A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer for dividing the semiconductor substrate into a field region and an active region; a main gate on a predetermined portion of the active region of the semiconductor substrate; a sidewall gate at both sides of the main gate on the semiconductor substrate; a main gate insulating layer between the main gate and the semiconductor substrate; a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate; an insulating interlayer between the main gate and the sidewall gate; a first silicide layer on the surface of the main gate and the sidewall gate, to electrically connect the main gate with the sidewall gate; and source and drain regions at both sides of the sidewall gate in the active region of the semiconductor substrate.

Abstract translation: 公开了一种半导体器件及其制造方法，其中从主栅极到侧壁栅极形成一条线，使得可以将纳米级以上的晶体管缩放，并且半导体器件包括半导体衬底; 用于将半导体衬底分成场区域和有源区域的器件隔离层; 在半导体衬底的有源区的预定部分上的主栅极; 在半导体衬底上的主栅极的两侧的侧壁栅极; 主栅极和半导体衬底之间的主栅极绝缘层; 侧壁栅极和半导体衬底之间的侧壁栅极绝缘层; 在主栅极和侧壁栅极之间的绝缘中间层; 在主栅极和侧壁栅极的表面上的第一硅化物层，以将主栅极与侧壁栅极电连接; 以及在半导体衬底的有源区域中的侧壁栅极的两侧的源极和漏极区域。

公开(公告)号：US07217973B2

公开(公告)日：2007-05-15

申请号：US10962818

申请日：2004-10-07

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/115 ,  H01L29/66484 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66643 ,  H01L29/7831 ,  H01L29/7833

Abstract: A semiconductor device and a fabricating method thereof are disclosed. The semiconductor device includes polysilicon gate electrodes, a gate oxide layer, sidewall floating gates, a block oxide layer, source/drain areas, and sidewall spacers. In addition, the method includes the steps of: forming a block dielectric layer and a sacrificial layer on a semiconductor substrate; forming trenches by etching the sacrificial layer; forming sidewall floating gates on lateral faces of the trenches; forming a block oxide layer on the sidewall floating gates; forming polysilicon gate electrodes by a patterning process; removing the sacrificial layer; forming source/drain areas by implanting impurity ions into the resulting structure; injecting carriers or electric charges into the sidewall floating gates; and forming spacers on lateral faces of the polysilicon gate electrodes and the sidewall floating gates.

Abstract translation: 公开了一种半导体器件及其制造方法。 半导体器件包括多晶硅栅电极，栅极氧化层，侧壁浮置栅极，块状氧化物层，源极/漏极区域和侧壁间隔物。 此外，该方法包括以下步骤：在半导体衬底上形成块介质层和牺牲层; 通过蚀刻牺牲层形成沟槽; 在沟槽的侧面上形成侧壁浮动栅; 在所述侧壁浮动栅上形成块状氧化物层; 通过图案化工艺形成多晶硅栅电极; 去除牺牲层; 通过将杂质离子注入到所得结构中来形成源极/漏极区域; 将载体或电荷注入到侧壁浮动门中; 以及在多晶硅栅极电极和侧壁浮动栅极的侧面上形成间隔物。

公开(公告)号：US07177185B2

公开(公告)日：2007-02-13

申请号：US11023425

申请日：2004-12-29

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: G11C11/34

CPC classification number: G11C16/0458

Abstract: A non-volatile memory device having a unit cell, the unit cell including a transistor, word lines, a first bit line and a second bit line. The transistor includes a gate oxide layer on a substrate, polysilicon gate, sidewall floating gates, block oxide layers formed between the polysilicon gate and sidewall floating gates, the block oxide layers also comprising first block oxide layer and second block oxide layer, and source and drain regions. The word lines are vertically placed on the substrate and connected to the polysilicon gate. The first bit line is orthogonally placed to the word lines and connected to the source region and a second bit line is orthogonally placed to the word lines and connected to the drain region.

Abstract translation: 一种具有单位单元的非易失性存储器件，该单元包括晶体管，字线，第一位线和第二位线。 晶体管包括在衬底上的栅极氧化层，多晶硅栅极，侧壁浮动栅极，形成在多晶硅栅极和侧壁浮置栅极之间的块状氧化物层，所述块状氧化物层还包括第一块状氧化物层和第二块状氧化物层， 漏区。 字线垂直放置在基板上并连接到多晶硅栅极。 第一位线被正交放置到字线并连接到源极区域，第二位线被正交地放置到字线并连接到漏极区域。

公开(公告)号：US07154143B2

公开(公告)日：2006-12-26

申请号：US10981164

申请日：2004-11-04

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L29/792

CPC classification number: H01L21/28194 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/517 ,  H01L29/792

Abstract: Non-volatile memory devices and methods of fabricating the same are disclosed. A disclosed non-volatile memory device includes: a tunnel oxide layer formed on a semiconductor substrate and having an energy bandgap; a storage oxide layer formed on the tunnel oxide layer and having an energy bandgap which is smaller than the energy bandgap of the tunnel oxide layer; a block oxide layer formed on the storage oxide layer and having an energy bandgap greater than the energy bandgap of the storage oxide layer; and a gate formed on the block oxide layer.

Abstract translation: 公开了非易失性存储器件及其制造方法。 所公开的非易失性存储器件包括：形成在半导体衬底上并具有能带隙的隧道氧化物层; 形成在所述隧道氧化物层上并且具有小于所述隧道氧化物层的能带隙的能带隙的存储氧化物层; 形成在所述存储氧化物层上并具有大于所述存储氧化物层的能带隙的能带隙的块状氧化物层; 以及形成在所述块状氧化物层上的栅极。