公开(公告)号：US08451660B2

公开(公告)日：2013-05-28

申请号：US12978865

申请日：2010-12-27

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: G11C16/04

CPC classification number: H01L27/11558 ,  G11C16/0441 ,  G11C2216/10

Abstract: A semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first conductive type well and a second conductive type well disposed on and/or over a semiconductor substrate; a first gate and a second gate disposed on and/or over the first conductive type well and the second conductive type well, respectively; a second conductive type first ion implantation region disposed in the first conductive type well at one side of the first gate and a second conductive type second ion implantation region disposed in the first conductive type well at the other side of the first gate; a first conductive type first ion implantation region disposed in the second conductive type well at one side of the second gate and a first conductive type second ion implantation region disposed in the second conductive type well at the other side of the second gate; and a line electrically connecting the second conductive type second ion implantation region with the first conductive type first ion implantation region.

Abstract translation: 半导体存储器件及其制造方法。 半导体存储器件包括第一导电型阱和布置在半导体衬底上和/或之上的第二导电类型阱; 分别设置在第一导电类型阱和第二导电类型阱上和/或上方的第一栅极和第二栅极; 设置在第一栅极一侧的第一导电类型阱中的第二导电型第一离子注入区和设置在第一栅极另一侧的第一导电类型阱中的第二导电型第二离子注入区; 设置在第二栅极一侧的第二导电类型阱中的第一导电型第一离子注入区和设置在第二栅极另一侧的第二导电类型阱中的第一导电型第二离子注入区; 以及将第二导电型第二离子注入区与第一导电型第一离子注入区电连接的线。

公开(公告)号：US07688642B2

公开(公告)日：2010-03-30

申请号：US11800555

申请日：2007-05-04

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: G11C11/34

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  G11C16/10 ,  H01L21/28282 ,  H01L29/792

Abstract: Provided are a SONGS type nonvolatile or flash memory device and related programming/erasing methods. The device has a deep well region of a first conductive type that isolates a well region of a second conductive type from a substrate to enhance programming and erasing operation characteristics. In the erasing method, first electrons are erased by one of Hot Hole Injection (e.g., gate-to-drain Hot Hole Injection) or tunneling in a first step, and second electrons that are not erased in the first step are erased by the other of tunneling (e.g., gate-to-body tunneling) or HHI in a second step. Preferably, a time gap intervenes between the first and second steps.

Abstract translation: 提供了一种SONGS型非易失性或闪存设备和相关的编程/擦除方法。 该器件具有第一导电类型的深阱区，其将第二导电类型的阱区与衬底隔离以增强编程和擦除操作特性。 在擦除方法中，第一步中的第一个电子被热孔注入（例如栅极到漏极热孔注入）或隧道中的一个擦除，第一步中未被擦除的第二个电子被其他的 隧道（例如，门对体隧道）或HHI在第二步。 优选地，时间间隙介于第一和第二步骤之间。

公开(公告)号：US07374989B2

公开(公告)日：2008-05-20

申请号：US11823321

申请日：2007-06-26

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42336

Abstract: Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed within the epitaxial layer to expose the first source; a floating gate device formed inside the opening; and a select gate device formed on the epitaxial layer at a distance from the floating gate device.

Abstract translation: 公开了闪存及其制造方法。 所示示例性闪存包括形成在半导体衬底内的第一源; 形成在所述半导体衬底的上表面上的外延层; 形成在所述外延层内以露出所述第一源的开口; 形成在开口内的浮栅装置; 以及在距离浮动栅极器件一定距离的外延层上形成的选择栅极器件。

公开(公告)号：US07336534B2

公开(公告)日：2008-02-26

申请号：US11024468

申请日：2004-12-30

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: G11C11/34

CPC classification number: G11C14/0063 ,  G11C14/00 ,  G11C16/0466

Abstract: A non-volatile memory device and drive method thereof uses a voltage bias condition to enable an electronic device to normally operate without employing a specific transistor, e.g., a recall transistor. The non-volatile memory device performs its function normally without the recall transistor, and by which a degree of cell integration can be considerably raised. A SRAM latch is controlled by the logic circuit, a SONOS (silicon-oxide-nitride-oxide-silicon) transistor is electrically connected to a Vcc node of the electronic device to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power, and a pass transistor controls read, program, and erase operations of the SONOS transistor.

Abstract translation: 非易失性存储器件及其驱动方法使用电压偏置条件使得电子器件能够正常工作，而不使用特定的晶体管，例如调用晶体管。 非易失性存储器件在没有调用晶体管的情况下正常地执行其功能，并且可以显着提高单元集成程度。 SRAM锁存器由逻辑电路控制，SONOS（氧化硅 - 氧化物 - 氧化物 - 硅）晶体管电连接到电子设备的Vcc节点，以根据转向存储SRAM锁存器的高/低状态 - 或关断电源状态，并且通过晶体管控制SONOS晶体管的读取，编程和擦除操作。

公开(公告)号：US07253468B2

公开(公告)日：2007-08-07

申请号：US10971585

申请日：2004-10-22

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L29/788 ,  H01L29/76

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42336

Abstract: Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed within the epitaxial layer to expose the first source; a floating gate device formed inside the opening; and a select gate device formed on the epitaxial layer at a distance from the floating gate device.

公开(公告)号：US20070148872A1

公开(公告)日：2007-06-28

申请号：US11641791

申请日：2006-12-20

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: The method of forming a floating gate array of a flash memory device includes: (a) forming a plurality of device isolations, which define active device regions, in a semiconductor substrate, the device isolations being formed such that upper portions thereof protrude from a surface of the substrate by a predetermined height; (b) forming tunnel oxide layers in the active device regions; (c) forming a floating gate-forming layer throughout an entire region of the substrate, including regions in which the plurality of device isolations and the active device regions are formed, the floating gate-forming layer being formed such that grooves are formed along the active device regions; (d) filling the grooves formed on the floating gate-forming layer with masking materials; and (e) patterning the floating gate-forming layer, using the masking materials filling the grooves as an etching mask.

Abstract translation: 形成闪存器件的浮置栅极阵列的方法包括：（a）在半导体衬底中形成限定有源器件区域的多个器件隔离，器件隔离形成为使得其上部从表面突出 的基板; （b）在有源器件区域中形成隧道氧化物层; （c）在基板的整个区域中形成浮栅形成层，包括形成多个器件隔离区和有源器件区的区域，形成浮栅形成层，沿着沿着 有源器件区域; （d）用掩蔽材料填充形成在浮栅形成层上的槽; 和（e）使用填充凹槽的掩模材料作为蚀刻掩模来图案化浮栅形成层。

公开(公告)号：US06996012B2

公开(公告)日：2006-02-07

申请号：US11024197

申请日：2004-12-29

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: G11C16/34

CPC classification number: G11C11/5621 ,  G11C16/10 ,  G11C16/3486

Abstract: A non-volatile memory device and a method for driving the same prevent an excessive electron erasing phenomenon without additional components. Each memory cell includes a tunnel oxide layer, a floating gate, a control gate connected to a word line, first and second oxide layers formed between the floating gate and the control gate, and first and second impurity diffusion layers formed in a semiconductor substrate at both sides of the floating gate and connected to a common line and a bit line.

Abstract translation: 非易失性存储器件及其驱动方法防止过多的电子擦除现象而没有额外的部件。 每个存储单元包括隧道氧化物层，浮置栅极，连接到字线的控制栅极，形成在浮置栅极和控制栅极之间的第一和第二氧化物层，以及形成在半导体衬底中的第一和第二杂质扩散层 浮动门的两边连接到一条公共线和一条位线。

公开(公告)号：US06977201B2

公开(公告)日：2005-12-20

申请号：US10747619

申请日：2003-12-30

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L21/28194 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/517

Abstract: A method for fabricating a flash memory includes forming a tunnel oxide layer by depositing a material with a conduction band energy level lower than that of SiO2 on a semiconductor substrate; forming a floating gate by depositing polysilicon on the tunnel oxide layer; forming an intergate dielectric layer on the floating gate; forming a control gate on the intergate dielectric layer; forming a gate electrode by patterning the tunnel oxide layer, the floating gate, the intergate dielectric layer and the control gate; and forming a source/drain region by implanting impurities into the substrate using the gate electrode as a mask.

Abstract translation: 制造闪速存储器的方法包括通过在半导体衬底上沉积具有低于SiO 2 2的导带能级的材料形成隧道氧化物层; 通过在隧道氧化物层上沉积多晶硅来形成浮栅; 在浮栅上形成隔间介电层; 在所述隔间介电层上形成控制栅极; 通过图案化隧道氧化物层，浮置栅极，栅间电介质层和控制栅极来形成栅电极; 以及通过使用栅极电极作为掩模将杂质注入到衬底中来形成源极/漏极区域。

公开(公告)号：US20120155176A1

公开(公告)日：2012-06-21

申请号：US12978865

申请日：2010-12-27

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: G11C16/04 ,  H01L27/115

CPC classification number: H01L27/11558 ,  G11C16/0441 ,  G11C2216/10

Abstract: A semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first conductive type well and a second conductive type well disposed on and/or over a semiconductor substrate; a first gate and a second gate disposed on and/or over the first conductive type well and the second conductive type well, respectively; a second conductive type first ion implantation region disposed in the first conductive type well at one side of the first gate and a second conductive type second ion implantation region disposed in the first conductive type well at the other side of the first gate; a first conductive type first ion implantation region disposed in the second conductive type well at one side of the second gate and a first conductive type second ion implantation region disposed in the second conductive type well at the other side of the second gate; and a line electrically connecting the second conductive type second ion implantation region with the first conductive type first ion implantation region.

Abstract translation: 半导体存储器件及其制造方法。 半导体存储器件包括第一导电型阱和布置在半导体衬底上和/或之上的第二导电类型阱; 分别设置在第一导电类型阱和第二导电类型阱上和/或上方的第一栅极和第二栅极; 设置在第一栅极一侧的第一导电类型阱中的第二导电型第一离子注入区和设置在第一栅极另一侧的第一导电类型阱中的第二导电型第二离子注入区; 设置在第二栅极一侧的第二导电类型阱中的第一导电型第一离子注入区和设置在第二栅极另一侧的第二导电类型阱中的第一导电型第二离子注入区; 以及将第二导电型第二离子注入区与第一导电型第一离子注入区电连接的线。

公开(公告)号：US07605036B2

公开(公告)日：2009-10-20

申请号：US11641791

申请日：2006-12-20

Applicant: Jin Hyo Jung

Inventor： Jin Hyo Jung

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: The method of forming a floating gate array of a flash memory device includes: (a) forming a plurality of device isolations, which define active device regions, in a semiconductor substrate, the device isolations being formed such that upper portions thereof protrude from a surface of the substrate by a predetermined height; (b) forming tunnel oxide layers in the active device regions; (c) forming a floating gate-forming layer throughout an entire region of the substrate, including regions in which the plurality of device isolations and the active device regions are formed, the floating gate-forming layer being formed such that grooves are formed along the active device regions; (d) filling the grooves formed on the floating gate-forming layer with masking materials; and (e) patterning the floating gate-forming layer, using the masking materials filling the grooves as an etching mask.

Abstract translation: 形成闪存器件的浮置栅极阵列的方法包括：（a）在半导体衬底中形成限定有源器件区域的多个器件隔离，器件隔离形成为使得其上部从表面突出 的基板; （b）在有源器件区域中形成隧道氧化物层; （c）在基板的整个区域中形成浮栅形成层，包括形成多个器件隔离区和有源器件区的区域，形成浮栅形成层，沿着沿着 有源器件区域; （d）用掩蔽材料填充形成在浮栅形成层上的槽; 和（e）使用填充凹槽的掩模材料作为蚀刻掩模来图案化浮栅形成层。