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公开(公告)号：US08171448B2
公开(公告)日：2012-05-01
申请号：US12129777
申请日：2008-05-30
申请人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
发明人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
IPC分类号： G06F17/50
CPC分类号： G06F11/0757
摘要： A design structure for a livelock resolution circuit is provided. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.
摘要翻译： 提供了一种用于动态锁分辨率电路的设计结构。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间没有进行任何进展，则确定已经发生了挂起状况。
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公开(公告)号：US20120057637A1
公开(公告)日：2012-03-08
申请号：US12874564
申请日：2010-09-02
IPC分类号： H04N7/24
CPC分类号： H04N19/436 , H04N19/13 , H04N19/44 , H04N19/91
摘要： Mechanisms for performing decoding of context-adaptive binary arithmetic coding (CABAC) encoded data. The mechanisms receive, in a first single instruction multiple data (SIMD) vector register of the data processing system, CABAC encoded data of a bit stream. The CABAC encoded data comprises a value to be decoded and bit stream state information. The mechanisms receive, in a second SIMD vector register of the data processing system, CABAC decoder context information. The mechanisms process the value, the bit stream state information, and the CABAC decoder context information in a non-recursive manner to generate a decoded value, updated bit stream state information, and updated CABAC decoder context information. The mechanisms store, in a third SIMD vector register, a result vector that combines the decoded value, updated bit stream state information, and updated CABAC decoder context information. The mechanisms use the decoded value to generate a video output on the data processing system.
摘要翻译： 用于执行上下文自适应二进制算术编码（CABAC）编码数据的解码的机制。 这些机制在数据处理系统的第一个单指令多数据（SIMD）向量寄存器中接收位数据流的CABAC编码数据。 CABAC编码数据包括要解码的值和位流状态信息。 该机制在数据处理系统的第二SIMD向量寄存器中接收CABAC解码器上下文信息。 该机制以非递归方式处理值，比特流状态信息和CABAC解码器上下文信息，以生成解码值，更新的比特流状态信息和更新的CABAC解码器上下文信息。 该机制在第三SIMD向量寄存器中存储组合解码值，更新位流状态信息和更新的CABAC解码器上下文信息的结果向量。 这些机制使用解码的值在数据处理系统上生成视频输出。
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公开(公告)号：US08128498B2
公开(公告)日：2012-03-06
申请号：US11425452
申请日：2006-06-21
IPC分类号： A63F9/22
CPC分类号： G06N3/006 , A63F13/49 , A63F13/55 , A63F13/822 , A63F13/85 , A63F2300/537 , A63F2300/575 , G07F17/32
摘要： A mechanism is provided for configuring offline player behavior within a persistent world game. A player agent for an offline player includes an event monitor that monitors for events that occur in a persistent virtual world maintained by a game server. When a game event occurs that triggers an offline player rule, the player agent may generate game events on behalf of the offline player. The player agent may also receive messages from an offline player. The messages may include commands for adding, removing, or editing offline player rules. A message may also include a command to view a list of rules or fire a one-time execution of a rule upon receipt. Therefore, a player may contribute to the persistent virtual world even when offline by sending commands using a messaging client or Web browser.
摘要翻译： 提供了一种用于在持久化世界游戏中配置离线玩家行为的机制。 用于离线播放器的播放器代理包括事件监视器，其监视由游戏服务器维护的持久虚拟世界中发生的事件。 当发生触发离线玩家规则的游戏事件时，玩家代理可以代表离线玩家生成游戏事件。 播放器代理也可以从离线播放器接收消息。 消息可能包括用于添加，删除或编辑离线播放器规则的命令。 消息还可以包括查看规则列表的命令或者在接收到一次规则执行时触发。 因此，即使当通过使用消息传递客户端或Web浏览器发送命令进行脱机时，玩家也可以对持久虚拟世界作出贡献。
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公开(公告)号：US07730279B2
公开(公告)日：2010-06-01
申请号：US12429676
申请日：2009-04-24
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
IPC分类号： G06F12/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译： 提供了用于限制处理器的本地存储器的大小的系统。 与用于设置本地存储大小限制的处理器相关联地提供设施。 该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。 当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。 当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为 用于访问本地存储。
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公开(公告)号：US07539787B2
公开(公告)日：2009-05-26
申请号：US11252532
申请日：2005-10-18
申请人： Michael N. Day , Charles R. Johns , Barry L. Minor
发明人： Michael N. Day , Charles R. Johns , Barry L. Minor
CPC分类号： G06F13/28
摘要： A buffer, a method, and a computer program product for DMA transfers are provided that are designed to save memory space within a local memory of a processor. The buffer is a return buffer with a portion reserved for DMA lists. A DMA controller accomplishes DMA transfers by: reading address elements from a DMA list located in the DMA list portion; reading the corresponding data from system memory; and copying the corresponding data to the return buffer portion. This buffer saves space because when the buffer begins to fill up the corresponding return data can overwrite the data in the DMA list. Accordingly, the DMA list overlays on top of the return buffer, such that the return data can destruct the DMA list and the extra storage space for the DMA list is saved.
摘要翻译： 提供了用于DMA传输的缓冲器，方法和计算机程序产品，其被设计为在处理器的本地存储器内节省存储器空间。 缓冲区是具有为DMA列表保留的部分的返回缓冲区。 DMA控制器通过以下方式完成DMA传输：从位于DMA列表部分的DMA列表读取地址元素; 从系统内存读取相应的数据; 并将相应的数据复制到返回缓冲器部分。 此缓冲区可节省空间，因为当缓冲区开始填满相应的返回数据时，可以覆盖DMA列表中的数据。 因此，DMA列表覆盖在返回缓冲器的顶部，使得返回数据可以破坏DMA列表，并且保存DMA列表的额外的存储空间。
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公开(公告)号：US07500039B2
公开(公告)日：2009-03-03
申请号：US11207971
申请日：2005-08-19
CPC分类号： G06F13/24
摘要： A method for communicating with a processor event facility is provided. The method makes use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种与处理器事件设施通信的方法。 该方法利用通道接口作为与处理器事件设施通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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47.发明申请公开(公告)号：US20080288757A1
公开(公告)日：2008-11-20
申请号：US12129114
申请日：2008-05-29
IPC分类号： G06F9/38
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901
摘要： A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于在处理器和外部设备之间传送指令和数据的机制。 该机制利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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48.发明授权Method and system for automatically assigning memory modules of different predetermined capacities to contiguous segments of a linear address range 失效用于将具有不同预定容量的存储器模块自动分配给线性地址范围的连续段的方法和系统
公开(公告)号：US4908789A
公开(公告)日：1990-03-13
申请号：US034236
申请日：1987-04-01
IPC分类号： G06F12/06
CPC分类号： G06F12/0653 , G06F12/0684
摘要： A method and system for addressing memory of an information handling system in which the memory comprises a plurality of memory banks, each of which can support a plurality of different predetermined size memory modules. The sizes of the different modules are multiples of the module having the smallest size. In the embodiment described, two different sizes are employed, a 256K capacity module and a 1 Meg. capacity module, either of which can be installed in 1 of 4 memory banks. The maximum addressable address range is therefore 4 Meg. while the minimum memory is 256K. The address range can be increased in increments of 256K corresponding to 1 segment to a total of 16 contiguous segments or 4 Meg. A memory address bus comprising 22 lines is employed in the system. The 20 low order lines address each bank simultaneously. A converter converts the 4 high order address bits 22-19 to 16 sequentially ordered segment lines. A matrix of similar logic cells consisting of combinatorial logic processes each segment line to develop memory bank select signals in accordance with size signals obtained from the modules and supplied to the cells in the first row of the matrix which then provide modified size signals to remaining cells in the respective columns of the matrix. Contiguous address segments are provided from the minimum to the maximum range for every possible combination of memory modules installable in the four banks.
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公开(公告)号：US09983874B2
公开(公告)日：2018-05-29
申请号：US12132430
申请日：2008-06-03
申请人： Charles R. Johns
发明人： Charles R. Johns
CPC分类号： G06F9/30043 , G06F8/458 , G06F9/30 , G06F9/30087 , G06F9/3836 , G06F12/00
摘要： A design structure for a circuit function that implements a load when reservation lost instruction for performing cacheline polling is disclosed. Initially, a first process requests an action to be performed by a second process. The request is made via a store operation to a cacheable memory location. The first process then reads the cacheable memory location via a conditional load operation to determine whether or not the requested action has been completed by the second process, and the first process sets a reservation at the cacheable memory location if the requested action has not been completed by the second process. The conditional load operation of the first process is stalled until the reservation at the cacheable memory location has been lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.
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公开(公告)号：US08918553B2
公开(公告)日：2014-12-23
申请号：US13488856
申请日：2012-06-05
申请人： Brian K. Flachs , Harm P. Hofstee , Charles R. Johns , Matthew E. King , John S. Liberty , Brad W. Michael
发明人： Brian K. Flachs , Harm P. Hofstee , Charles R. Johns , Matthew E. King , John S. Liberty , Brad W. Michael
CPC分类号： G06F9/30087 , G06F9/3877 , G06F13/1663 , G06F13/28
摘要： A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.
摘要翻译： 提供了编程作为多线程处理器操作的直接存储器访问引擎的机制。 从与直接存储器访问引擎相关联的本地存储器中的主机处理器接收多个程序。 在来自主机处理器的直接存储器访问引擎中接收到指示将要执行位于本地存储器中的多个程序的请求。 直接存储器访问引擎在主机处理器的干预下执行多个程序中的两个或多个。 当多个程序中的两个或更多个程序中的每一个完成执行时，直接存储器访问引擎向主处理器发送指示程序已经完成执行的完成通知。
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