公开(公告)号：US07240322B2

公开(公告)日：2007-07-03

申请号：US10907494

申请日：2005-04-04

申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US07239167B2

公开(公告)日：2007-07-03

申请号：US11382601

申请日：2006-05-10

申请人： John M. Cohn ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

发明人： John M. Cohn ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

IPC分类号： G01R31/02

CPC分类号： G01R31/31727 ,  G01R31/025 ,  G01R31/30 ,  G01R31/31725

摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

摘要翻译： 公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。 屏蔽与时钟信号接线相邻，接地线将屏蔽接地。 屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。 本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

公开(公告)号：US07188322B2

公开(公告)日：2007-03-06

申请号：US10906591

申请日：2005-02-25

申请人： John M. Cohn ,  Jason Hibbeler ,  Anthony K. Stamper ,  Jed H. Rankin

发明人： John M. Cohn ,  Jason Hibbeler ,  Anthony K. Stamper ,  Jed H. Rankin

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.

摘要翻译： 提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。 该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。 符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。 布局迁移工具可用于修改现有布局，以实施新的网格要求。

公开(公告)号：US07107469B2

公开(公告)日：2006-09-12

申请号：US10604328

申请日：2003-07-11

申请人： Rafael Blanco ,  John M. Cohn ,  Kenneth J. Goodnow ,  Douglas W. Stout ,  Sebastian T. Ventrone

发明人： Rafael Blanco ,  John M. Cohn ,  Kenneth J. Goodnow ,  Douglas W. Stout ,  Sebastian T. Ventrone

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y02D10/171

摘要： A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

摘要翻译： 一种在半导体器件上处理数据的结构和相关方法，包括形成在半导体器件上的输入岛，处理岛和输出岛。 输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。 处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。 输出岛适于由第二规定电压供电。 处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。 第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。

公开(公告)号：US07095063B2

公开(公告)日：2006-08-22

申请号：US10249779

申请日：2003-05-07

申请人： John M. Cohn ,  Kevin M. Grosselfinger ,  William F. Smith ,  Paul S. Zuchowski

发明人： John M. Cohn ,  Kevin M. Grosselfinger ,  William F. Smith ,  Paul S. Zuchowski

IPC分类号： H01L27/10

CPC分类号： H01L27/11803

摘要： A multiple supply gate array structure facilitated by the provision of a shared n-well and an isolated n-well is described. The gate array structure allows implementation of a single voltage circuit or a multiple voltage circuit. In addition, the gate array structure allows metal reprogram to provide standard logic functions, or special logic functions such as a buffer function for a signal crossing a voltage island boundary. Other special logic functions may include, for example, a level-shifter function or a fence-hold function.

摘要翻译： 描述了通过提供共享n阱和隔离的n阱来促进的多电源栅极阵列结构。 门阵列结构允许实现单电压电路或多电压电路。 此外，门阵列结构允许金属重新编程提供标准逻辑功能，或特殊逻辑功能，例如跨越电压岛边界的信号的缓冲功能。 其他特殊逻辑功能可以包括例如电平转换器功能或栅栏保持功能。

公开(公告)号：US07089514B2

公开(公告)日：2006-08-08

申请号：US10710879

申请日：2004-08-10

申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Francis Gravel ,  Leendert M. Huisman ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Kenneth Rowe ,  Thomas G. Sopchak ,  David E. Sweenor

发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Francis Gravel ,  Leendert M. Huisman ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Kenneth Rowe ,  Thomas G. Sopchak ,  David E. Sweenor

IPC分类号： G06F17/50

CPC分类号： G01R31/31718 ,  G01R31/318342

摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.

摘要翻译： 一种半导体芯片缺陷诊断方法。 该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

公开(公告)号：US06825711B2

公开(公告)日：2004-11-30

申请号：US10249684

申请日：2003-04-30

申请人： John M. Cohn ,  Kenneth J. Goodnow ,  Scott W. Gould ,  Douglas W. Stout ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Kenneth J. Goodnow ,  Scott W. Gould ,  Douglas W. Stout ,  Sebastian T. Ventrone

IPC分类号： G05F110

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172

摘要： An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.

摘要翻译： 一种集成电路，方法和系统，提供更精细的粒度动态电压控制，无需性能损失。 本发明提供了用于在特定周期中动态地改变关键路径上的至少一个级的电压电平的装置。 以这种方式，可以为给定期望的阶段提供最佳电压。

公开(公告)号：US06751744B1

公开(公告)日：2004-06-15

申请号：US09475799

申请日：1999-12-30

申请人： Robert J. Allen ,  John M. Cohn ,  David J. Hathaway

发明人： Robert J. Allen ,  John M. Cohn ,  David J. Hathaway

IPC分类号： G06F112

CPC分类号： G06F17/504 ,  G06F2217/78

摘要： A method for checking integrated circuit designs comprising the steps of calculating a first performance parameter by analyzing the network's sensitivity to a signal applied to the network; comparing the first performance parameter to one or more rules to determine a first pass condition and writing the value of first performance parameter to a netlist file in response to a pass to the first pass condition; followed by calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing the second performance parameter to the netlist file in response to a pass to said second pass condition or writing an error flag to the netlist file in response to a fail to said second pass condition is disclosed. The method, at each step, decides if a quick to calculate parameter provides sufficient design margin or if a more accurate but longer to calculate parameter is required.

摘要翻译： 一种用于检查集成电路设计的方法，包括以下步骤：通过分析网络对施加到网络的信号的灵敏度来计算第一性能参数; 将所述第一性能参数与一个或多个规则进行比较以确定第一通过条件，并响应于所述第一通过条件的传递将所述第一性能参数的值写入网表文件; 随后基于第一网络模型计算第二性能参数，以响应于所述第一通过条件的失败来确定第二通过条件，并响应于所述第二通过条件的通过将所述第二性能参数写入所述网表文件，或 公开了响应于所述第二通过条件的失败向网表文件写入错误标志。 该方法在每个步骤中决定快速计算参数是否提供足够的设计余量，或者是否需要更准确但更长的计算参数。

公开(公告)号：US06687883B2

公开(公告)日：2004-02-03

申请号：US09750969

申请日：2000-12-28

申请人： John M. Cohn ,  Alvar A. Dean ,  David J. Hathaway ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  David J. Hathaway ,  Sebastian T. Ventrone

IPC分类号： G06F1750

CPC分类号： G06F1/3243 ,  G06F1/3203 ,  Y02D10/152 ,  Y02D50/20

摘要： A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify “sleep states” for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a “sleep state”; and forcing the determined net to the determined value determined portion of that “sleep state”.

摘要翻译： 一种用于减少逻辑网络的泄漏功率的方法，包括以下步骤：使用（可观察性）不关心信息以识别各个网络的“睡眠状态”; 基于概率分析确定至少一个网络，其中通过在“睡眠状态”的至少一部分期间将网络强制为特定值来减少预期功率消耗; 并将所确定的网络强制为所述“睡眠状态”的确定值确定部分。

公开(公告)号：US06523159B2

公开(公告)日：2003-02-18

申请号：US09761464

申请日：2001-01-16

申请人： Kerry Bernstein ,  John M. Cohn ,  Jose L. P. Neves

发明人： Kerry Bernstein ,  John M. Cohn ,  Jose L. P. Neves

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.

摘要翻译： 一种用于在集成电路设计的平面布置阶段期间在集成电路中添加去耦电容的方法和相关程序存储产品。 本发明在平面图上覆盖电网，然后将电网划分为区域或宏。 对于每个区域或宏，确定支持电网电压所需的支持去耦电容值和固有电容值。 基于这些值，确定所需的去耦电容值及其去耦电容面积。 然后基于去耦电容面积交替设计。