摘要:
An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.
摘要:
A system and method for designing a low power ASIC using weighted net toggle information. In particular, the system and method includes a simulation system that executes a set of application test suites that is representative of the code that will likely run on the ASIC and weights each of the applications. The weighted net toggle information can then be evaluated and utilized to modify the ASIC design.
摘要:
According to the present invention, an automated method to tailor an ASIC core to meet the needs of an individual system on a chip design is disclosed. The preferred method starts with a technology-independent hardware description language (HDL) representation of the core des i on. This high-level design is subdivided into functions, or blocks. Blocks which cannot be removed without impacting the integrity of the core design an are ta b y ed with “must-keep” indicators. The execution of all application code that will employ the core is simulated on the high-level model. The simulation process accumulates information about what blocks in the model are used by the application code, and which are unused, information about which blocks are unused is combined with information about what blocks are not removable. The high-level core design is then tailored by deleting blocks in the core design that are both unused and removable. The tailored high-level design is then synthesized to a technology-dependent core design. The synthesis process substitutes gates for the blocks, propagating must-keep tags to all gates substituted for a block tagged with a “must-keep” indicator. The simulation of all application code is repeated on the low-level design, and accumulates information about which gates are unused by the application code. The low-level design is then tailored by deleting Yates in the core that are both unused and removable.
摘要:
An apparatus comprising a base macro, with fixed timing, surrounded by, and connected to, at least one selectable feature macro. The features of the apparatus may be selectively provided by connecting one or more of the selectable feature macros to the base macro.
摘要:
Redundant chip sections held in standby are substituted for chip sections that are at risk of over heating based on certain sensor signals. When these signals are received operations of the chip section at risk IS transferred to a redundant chip section and the chip section at risk is shut down. After the original chip section has cooled, it becomes available as a replacement chip section itself. The sensor signals may be based on temperature values, elapsed operation time, and number or rate of operations within a chip section.
摘要:
A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.
摘要:
A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.
摘要:
A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.
摘要:
A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands, creates a floorplan of the voltage islands, assesses the floorplan, repeats the partitioning and the creating of the floorplan depending upon a result of the assessing process, and outputs a voltage island specification list.
摘要:
In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.