公开(公告)号：US20080180153A1

公开(公告)日：2008-07-31

申请号：US12059238

申请日：2008-03-31

申请人： Manoj Sachdev ,  Shah M. Jahinuzzaman

发明人： Manoj Sachdev ,  Shah M. Jahinuzzaman

IPC分类号： H03K3/356

CPC分类号： G11C7/02 ,  G11C11/4125

摘要： A flip-flop circuit is provided with an improved robustness to radiation induced soft errors. The flip-flop cell comprises the following elements. A transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the transfer unit and a buffer unit coupled to the storage unit. The transfer unit includes a plurality of input nodes adapted to receive said at least one data signal and said at least one clock signal; a first output node for providing a sampled data signal in response to said at least one clock signal and said at least one data signal; and a second output node for providing a sampled inverse data signal, the sampled inverse data signal provided in response to said at least one clock signal and said at least one data signal. The storage unit comprises a first and a second storage nodes configured to receive and store the sampled data signal and the sampled inverse data signal. The storage unit comprises drive transistors configured to selectively couple one of the first and second storage nodes to ground; load transistors configured to selectively couple the other one of the first and second storage nodes to a power supply; and at least one stabilizer transistor configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error. The buffer unit provides an output sampled data signal as received from the storage unit.

摘要翻译： 触发器电路具有对辐射诱导的软错误的改进的鲁棒性。 触发器单元包括以下元件。 用于接收至少一个数据信号和至少一个时钟信号的传送单元，耦合到传送单元的存储单元和耦合到存储单元的缓冲单元。 传送单元包括适于接收所述至少一个数据信号和所述至少一个时钟信号的多个输入节点; 第一输出节点，用于响应于所述至少一个时钟信号和所述至少一个数据信号提供采样数据信号; 以及用于提供采样的反向数据信号的第二输出节点，响应于所述至少一个时钟信号和所述至少一个数据信号而提供的采样的反向数据信号。 存储单元包括被配置为接收和存储采样的数据信号和采样的反向数据信号的第一和第二存储节点。 存储单元包括被配置为选择性地将第一和第二存储节点之一耦合到地的驱动晶体管; 被配置为选择性地将第一和第二存储节点中的另一个耦合到电源的负载晶体管; 以及至少一个稳定器晶体管，被配置为提供对应的冗余存储节点并限制所述第一和第二存储节点之间的反馈，所述冗余存储节点在软错误的情况下能够恢复所述第一或第二存储节点。 缓冲单元提供从存储单元接收的输出采样数据信号。

公开(公告)号：US20080094925A1

公开(公告)日：2008-04-24

申请号：US11876223

申请日：2007-10-22

申请人： Manoj Sachdev ,  Shad M. Jahinuzzaman

发明人： Manoj Sachdev ,  Shad M. Jahinuzzaman

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C11/4125

摘要： A Static Random Access Memory (SRAM) cell is provided with an improved robustness to radiation induced soft errors. The SRAM cell comprises the following elements. First and second storage nodes are configured to store complementary voltages. Access transistors are configured to selectively couple the first and second storage nodes to a corresponding bit line. Drive transistors are configured to selectively couple one of the first and second storage nodes to ground. Load transistors are configured to selectively couple the other one of the first and second storage nodes to a power supply. At least one stabilizer transistor is configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes. The redundant storage node is capable of restoring the first or second storage nodes in case of a soft error.

摘要翻译： 静态随机存取存储器（SRAM）单元具有改善的对辐射诱导的软错误的鲁棒性。 SRAM单元包括以下元件。 配置第一和第二存储节点以存储互补电压。 接入晶体管被配置为选择性地将第一和第二存储节点耦合到对应的位线。 驱动晶体管被配置为选择性地将第一和第二存储节点之一耦合到地。 负载晶体管被配置为选择性地将第一和第二存储节点中的另一个耦合到电源。 至少一个稳定器晶体管被配置为提供对应的冗余存储节点并限制第一和第二存储节点之间的反馈。 冗余存储节点在软错误的情况下能够恢复第一或第二存储节点。

公开(公告)号：US06765414B2

公开(公告)日：2004-07-20

申请号：US10246377

申请日：2002-09-17

申请人： Ali Keshavarzi ,  Bhaskar P. Chatterjee ,  Ram Krishnamurthy ,  Manoj Sachdev

发明人： Ali Keshavarzi ,  Bhaskar P. Chatterjee ,  Ram Krishnamurthy ,  Manoj Sachdev

IPC分类号： H03K19096

CPC分类号： G01R31/2856 ,  G01R31/3016 ,  G01R31/31707 ,  G01R31/318502

摘要： A technique is described to allow testing of high-speed digital circuits using lower speed testing equipment, to circuits to be placed into a sleep mode, and to allow burn-in testing of digital circuits with minimal overhead in terms of silicon area or performance.

摘要翻译： 一种技术被描述为允许使用较低速度测试设备的高速数字电路，放置在睡眠模式中的电路进行测试，并允许在硅面积或性能方面具有最小开销的数字电路的老化测试。

公开(公告)号：US06369631B1

公开(公告)日：2002-04-09

申请号：US09608687

申请日：2000-06-29

申请人： Manoj Sachdev ,  Siva Narendra

发明人： Manoj Sachdev ,  Siva Narendra

IPC分类号： H03K3356

CPC分类号： H03K3/356156 ,  H03K3/356121

摘要： A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.

摘要翻译： 触发器电路使用由时钟信号激活的多输入条件转换器将输入数据的样本传送到保持器电路。 保持器电路信号被缓冲以提供触发器电路输出。

公开(公告)号：US06366147B2

公开(公告)日：2002-04-02

申请号：US09874866

申请日：2001-06-04

申请人： Manoj Sachdev ,  Siva Narenda

发明人： Manoj Sachdev ,  Siva Narenda

IPC分类号： H03K3289

CPC分类号： H03K3/356156 ,  H03K3/356121

摘要： A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.

公开(公告)号：US6134688A

公开(公告)日：2000-10-17

申请号：US551153

申请日：1997-11-26

申请人： Manoj Sachdev

发明人： Manoj Sachdev

IPC分类号： G01R31/317 ,  G01R31/28 ,  G01R31/30 ,  G01R31/3185 ,  G06F11/22

CPC分类号： G01R31/3008 ,  G01R31/3004 ,  G01R31/318541 ,  G01R31/318577

摘要： An electronic device, with a plurality of logic stages for functional collaboration, is provided with selection means for selectively operating the plurality of stages to form either a sequential logic circuit or a combinatorial logic circuit. This enables conversion of sequential logic circuitry into combinatorial logic circuitry for the purpose of effective I.sub.DDQ -testing.

摘要翻译： 具有用于功能协作的多个逻辑级的电子设备被提供有选择装置，用于选择性地操作多个级以形成顺序逻辑电路或组合逻辑电路。 这样就可以将顺序逻辑电路转换为组合逻辑电路，以实现有效的IDDQ测试。