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    High performance impulse flip-flops
    1.
    发明授权
    High performance impulse flip-flops 有权
    高性能脉冲触发器

    公开(公告)号：US06369631B1

    公开(公告)日：2002-04-09

    申请号：US09608687

    申请日：2000-06-29

    申请人： Manoj Sachdev ,  Siva Narendra

    发明人： Manoj Sachdev ,  Siva Narendra

    IPC分类号： H03K3356

    CPC分类号： H03K3/356156 ,  H03K3/356121

    摘要： A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.

    摘要翻译： 触发器电路使用由时钟信号激活的多输入条件转换器将输入数据的样本传送到保持器电路。 保持器电路信号被缓冲以提供触发器电路输出。

    Threshold voltage mismatch compensation sense-amplifiers for static random access memories with multiple differential inputs
    2.
    发明授权
    Threshold voltage mismatch compensation sense-amplifiers for static random access memories with multiple differential inputs 有权
    具有多个差分输入的静态随机存取存储器的阈值电压失配补偿读出放大器

    公开(公告)号：US09542995B2

    公开(公告)日：2017-01-10

    申请号：US14470866

    申请日：2014-08-27

    申请人： Manoj Sachdev ,  Jaspal Singh Shah

    发明人： Manoj Sachdev ,  Jaspal Singh Shah

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419

    摘要： Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors.

    摘要翻译： 描述用于存储器的感测放大器配置。 在这些配置中，差分输入与相应的位线电压成正比，从而能够实现低电压，可靠，更快的读出放大器操作。 公开的读出放大器还能够补偿感测晶体管之间的阈值失配。

    Asymmetric four-transistor SRAM cell
    3.
    发明授权
    Asymmetric four-transistor SRAM cell 失效
    非对称四晶体管SRAM单元

    公开(公告)号：US07643329B2

    公开(公告)日：2010-01-05

    申请号：US11621679

    申请日：2007-01-10

    申请人： Manoj Sachdev ,  Mohammad Sharifkhani

    发明人： Manoj Sachdev ,  Mohammad Sharifkhani

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C11/413

    摘要： An asymmetric Static Random Access Memory (SRAM) cell is provided. The SRAM cell comprises first and second storage nodes, drive transistors and access transistors. The first and second storage nodes are configured to store complementary voltages. The drive transistors are configured to selectively couple each of the first and second storage nodes to corresponding high and low voltage power supplies, and maintain a first logic state through a feedback loop. The access transistors are configured to selectively couple each of the first and second storage nodes to corresponding first and second bit-lines and maintain a second logic state through relative transistor leakage currents. A method for reading from and writing to the SRAM cell are also provided.

    摘要翻译： 提供了非对称静态随机存取存储器（SRAM）单元。 SRAM单元包括第一和第二存储节点，驱动晶体管和存取晶体管。 第一和第二存储节点被配置为存储互补电压。 驱动晶体管被配置为选择性地将第一和第二存储节点中的每一个耦合到相应的高电压和低电压电源，并且通过反馈回路保持第一逻辑状态。 存取晶体管被配置为选择性地将第一和第二存储节点中的每一个耦合到相应的第一和第二位线，并通过相对晶体管漏电流维持第二逻辑状态。 还提供了用于从SRAM单元读取和写入SRAM单元的方法。

    MOS master-slave flip-flop with reduced number of pass gates
    4.
    发明授权
    MOS master-slave flip-flop with reduced number of pass gates 失效
    MOS主从触发器，通过门数少

    公开(公告)号：US5831463A

    公开(公告)日：1998-11-03

    申请号：US696311

    申请日：1996-08-13

    申请人： Manoj Sachdev

    发明人： Manoj Sachdev

    IPC分类号： G01R31/30 ,  H03K3/037 ,  H03K19/173 ,  H03K3/3562

    CPC分类号： G01R31/3008 ,  G01R31/3004 ,  H03K3/0372

    摘要： A master-slave flip-flop has master and slave latches cascaded between an input and an output. Each latch has two inverters directly connected to one another head to tail. The latches are coupled via a buffer and a clock controlled pass gate. This architecture reduces the number of pass gates and clock lines, improves hold time and enhances I.sub.DDQ -testability with respect to known flip-flops.

    摘要翻译： 主从触发器具有在输入和输出之间级联的主从锁存器。 每个锁存器都有两个逆变器直接连接到另一个头尾。 锁存器通过缓冲器和时钟控制的通过门耦合。 该架构减少了通过门和时钟线的数量，改善了保持时间，并提高了与已知触发器的IDDQ可测试性。

    THRESHOLD VOLTAGE MISMATCH COMPENSATION SENSE-AMPLIFIERS FOR STATIC RANDOM ACCESS MEMORIES WITH MULTIPLE DIFFERENTIAL INPUTS
    7.
    发明申请
    THRESHOLD VOLTAGE MISMATCH COMPENSATION SENSE-AMPLIFIERS FOR STATIC RANDOM ACCESS MEMORIES WITH MULTIPLE DIFFERENTIAL INPUTS 审中-公开
    用于具有多种差分输入的静态随机存取存储器的阈值电压误差补偿

    公开(公告)号：US20160203856A1

    公开(公告)日：2016-07-14

    申请号：US14470866

    申请日：2014-08-27

    申请人： Manoj Sachdev ,  Jaspal Singh Shah

    发明人： Manoj Sachdev ,  Jaspal Singh Shah

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419

    摘要： Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors.

    摘要翻译： 描述用于存储器的感测放大器配置。 在这些配置中，差分输入与相应的位线电压成正比，从而能够实现低电压，可靠，更快的读出放大器操作。 公开的读出放大器还能够补偿感测晶体管之间的阈值失配。

    Sense-amplification with offset cancellation for static random access memories
    8.
    发明授权
    Sense-amplification with offset cancellation for static random access memories 有权
    用于静态随机存取存储器的偏移消除的感测放大

    公开(公告)号：US08488403B2

    公开(公告)日：2013-07-16

    申请号：US12757033

    申请日：2010-04-08

    申请人： Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

    发明人： Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

    IPC分类号： G11C7/02

    CPC分类号： G11C7/062 ,  G11C2207/063 ,  G11C2207/104

    摘要： An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on sensing nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers, amplifiers, and comparators.

    摘要翻译： 描述了用于感测放大的偏移消除方案。 该方案由通过多相定时选择性地耦合到高电压和低电压电平的晶体管组成。 这导致感兴趣的感测节点上的电压电平，其是晶体管不匹配的函数。 所产生的电压电平用于补偿晶体管失配，从而在存在工艺非理想性的情况下提高读出放大器的可靠性。 偏移消除方案适用于许多类型的读出放大器，放大器和比较器。

    SRAM cell without dedicated access transistors
    9.
    发明授权
    SRAM cell without dedicated access transistors 有权
    没有专用存取晶体管的SRAM单元

    公开(公告)号：US08072797B2

    公开(公告)日：2011-12-06

    申请号：US12494908

    申请日：2009-06-30

    申请人： Manoj Sachdev ,  David Rennie

    发明人： Manoj Sachdev ,  David Rennie

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least on wordline transistor and at least two supply transistors. The bitline transistor is configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column. The wordline transistor is configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column. The supply transistors are configured to selectively couple corresponding ones of the storage nodes to a supply voltage.

    摘要翻译： 描述了没有专用存取晶体管的静态随机存取存储器（SRAM）单元。 SRAM单元包括多个晶体管，其被配置为提供至少一对存储节点，用于存储由对应电压表示的互补逻辑值。 晶体管至少在字线晶体管和至少两个电源晶体管上包括至少一个位线晶体管。 位线晶体管被配置为选择性地将存储节点之一耦合到至少一个相应的位线，该位线用于由公共行或列之一中的SRAM单元共享的位线。 字线晶体管被配置为选择性地将另一个存储节点耦合到至少一个相应的字线，该字线由公共行或列中的另一个中的SRAM单元共享。 电源晶体管被配置为选择性地将相应的存储节点耦合到电源电压。

    Soft error robust flip-flops
    10.
    发明授权
    Soft error robust flip-flops 失效
    软错误鲁棒触发器

    公开(公告)号：US07714628B2

    公开(公告)日：2010-05-11

    申请号：US12059238

    申请日：2008-03-31

    申请人： Manoj Sachdev ,  Shah M. Jahinuzzaman

    发明人： Manoj Sachdev ,  Shah M. Jahinuzzaman

    IPC分类号： H03K3/356

    CPC分类号： G11C7/02 ,  G11C11/4125

    摘要： A flip-flop circuit is provided with an improved robustness to radiation induced soft errors. The flip-flop cell comprises the following elements. A transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the transfer unit and a buffer unit coupled to the storage unit. The transfer unit includes a plurality of input nodes adapted to receive said at least one data signal and said at least one clock signal; a first output node for providing a sampled data signal in response to said at least one clock signal and said at least one data signal; and a second output node for providing a sampled inverse data signal, the sampled inverse data signal provided in response to said at least one clock signal and said at least one data signal. The storage unit comprises a first and a second storage nodes configured to receive and store the sampled data signal and the sampled inverse data signal. The storage unit comprises drive transistors configured to selectively couple one of the first and second storage nodes to ground; load transistors configured to selectively couple the other one of the first and second storage nodes to a power supply; and at least one stabilizer transistor configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error. The buffer unit provides an output sampled data signal as received from the storage unit.

    摘要翻译： 触发器电路具有对辐射诱导的软错误的改进的鲁棒性。 触发器单元包括以下元件。 用于接收至少一个数据信号和至少一个时钟信号的传送单元，耦合到传送单元的存储单元和耦合到存储单元的缓冲单元。 传送单元包括适于接收所述至少一个数据信号和所述至少一个时钟信号的多个输入节点; 第一输出节点，用于响应于所述至少一个时钟信号和所述至少一个数据信号提供采样数据信号; 以及用于提供采样的反向数据信号的第二输出节点，响应于所述至少一个时钟信号和所述至少一个数据信号而提供的采样的反向数据信号。 存储单元包括被配置为接收和存储采样的数据信号和采样的反向数据信号的第一和第二存储节点。 存储单元包括被配置为选择性地将第一和第二存储节点之一耦合到地的驱动晶体管; 被配置为选择性地将第一和第二存储节点中的另一个耦合到电源的负载晶体管; 以及至少一个稳定器晶体管，被配置为提供对应的冗余存储节点并限制所述第一和第二存储节点之间的反馈，所述冗余存储节点在软错误的情况下能够恢复所述第一或第二存储节点。 缓冲单元提供从存储单元接收的输出采样数据信号。