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41.发明授权公开(公告)号：US07434264B2
公开(公告)日：2008-10-07
申请号：US10384024
申请日：2003-03-07
CPC分类号： G06F21/85 , G06F2221/2113 , G06F2221/2141
摘要： A flexible peripheral access protection mechanism within a data processing system (10, 100). In one embodiment, each master (14, 15) within the data processing system (10) includes a corresponding privilege level modifier (70, 74) and corresponding trust attributes (71, 72, 75, 76) for particular bus access types (e.g. read and write accesses). Also, in one embodiment, each peripheral (22, 24) within the data processing system (10) includes a corresponding trust attribute (80, 84), write protect indicator (81, 85), and a privilege protect indicator (82, 86). Therefore, in one embodiment, a bus access by a bus master to a peripheral is allowed when the bus master has the appropriate privilege level and appropriate level of trust required by the peripheral (and the peripheral is not write protected, if the bus access is a write access). Also, through the use of the privilege level modifiers, a the bus master can be forced to a particular privilege level for a particular bus access.
摘要翻译： 一种在数据处理系统（10,100）内的灵活的外围设备访问保护机制。 在一个实施例中，数据处理系统（10）内的每个主机（14,15）包括用于特定总线访问类型的对应的权限级别修改器（70,74）和对应的信任属性（71,72,75,76）（例如， 读写访问）。 此外，在一个实施例中，数据处理系统（10）内的每个外围设备（22,24）包括相应的信任属性（80,84），写入保护指示符（81,85）和特权保护指示符（82,86 ）。 因此，在一个实施例中，当总线主机具有适当的特权级别和外设所需的适当的信任级别（并且外围设备不被写保护时，如果总线访问是 写访问）。 此外，通过使用特权级别修改器，可以将总线主机强制为特定总线访问的特定权限级别。
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公开(公告)号：US20080126600A1
公开(公告)日：2008-05-29
申请号：US11513639
申请日：2006-08-31
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and device for processing direct memory access transfer requests is disclosed. The method includes executing a first transfer request associated with a channel of a DMA device, and determining if the next transfer request is associated with the same channel. If the next transfer request is associated with a different channel, the DMA device executes an arbitration process to determine the priority of the second transfer request relative to other pending transfer requests. If the next transfer request is associated with the same channel as the first transfer request, the DMA device executes the next transfer request without executing the normal arbitration process. By foregoing execution of the arbitration process when two transfer requests are associated with the same channel, the DMA device is able to begin execution of the transfer requests more quickly.
摘要翻译： 公开了一种用于处理直接存储器访问转移请求的方法和装置。 该方法包括执行与DMA设备的信道相关联的第一传送请求，以及确定下一传送请求是否与相同信道相关联。 如果下一个传输请求与不同的信道相关联，则DMA设备执行仲裁过程以确定第二传送请求相对于其他未决转发请求的优先级。 如果下一个传送请求与第一传送请求相同的信道相关联，则DMA设备执行下一个传送请求而不执行正常的仲裁过程。 当两个传输请求与相同的信道相关联时，通过执行仲裁过程，DMA设备能够更快地开始执行传送请求。
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43.发明授权Data processing system for controlling execution of a debug function and method thereof 失效用于控制调试功能的执行的数据处理系统及其方法
公开(公告)号：US6026501A
公开(公告)日：2000-02-15
申请号：US944655
申请日：1997-10-06
CPC分类号： G06F11/3648 , G06F11/3636
摘要： A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unte (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).
摘要翻译： 中央处理单元（2）和调试模块（10）执行并行操作，而不需要数据处理器（3）以特殊调试模式操作。 使用总线（25）在核心（9）和调试模块（10）之间传送数据，地址和控制信息允许调试模块（10）访问与中央处理单元相同的内部寄存器和存储器位置（ 2）。 虽然调试模块（10）和中央处理单元（2）都具有访问相同的内部寄存器和存储器位置的能力，但是当中央处理单元（2）可以修改存储在多个断点寄存器（50）中的值时， 设置多个控制寄存器（40）的CSR（图8）中的抑制处理器写入调试寄存器（IPW）位。 IPW位只能由外部开发系统（7）提供的命令修改。
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44.发明授权
公开(公告)号：US5737516A
公开(公告)日：1998-04-07
申请号：US520943
申请日：1995-08-30
CPC分类号： G06F11/364 , G06F11/3648
摘要： A data processor (3) executes a debug operation by minimally intruding on the real time operation of the data processor and without halting the data processor. The data processor implements a control register (40) which stores trigger response value for determining a function executed by the data processor when a breakpoint signal is asserted. The trigger response values indicates whether a central processing unit (2) of the data processor executes a special debug exception processing routine or suspends operation when the breakpoint signal is asserted.
摘要翻译： 数据处理器（3）通过最小程度地侵入数据处理器的实时操作并且不停止数据处理器来执行调试操作。 数据处理器实现一个控制寄存器（40），当控制断点信号被断言时，该控制寄存器（40）存储用于确定由数据处理器执行的功能的触发响应值。 触发响应值指示数据处理器的中央处理单元（2）是否执行特殊调试异常处理例程，或者当断点信号被断言时暂停操作。
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公开(公告)号：US5131086A
公开(公告)日：1992-07-14
申请号：US539381
申请日：1990-06-15
CPC分类号： G06F9/30032 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/325 , G06F9/3802 , G06F9/3806 , G06F9/382
摘要： A system and technique for providing early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both the instruction bits and the associated predecoded bits into a FIFO buffer to accumulate a plurality of such entries. Meanwhile, an operand execute pipeline retrieves such entries from the FIFO buffer as needed, using the predecoded instruction bits to rapidly decode and execute the instructions at rates determined by the instructions themselves. Delays due to cache misses are substantially or entirely masked, as the instructions and associated predecoded bits are loaded into the FIFO buffer more rapidly than they are retrieved from it, except during cache misses. A method is described for increasing the effective speed of executing a three operand construct. Another method is disclosed for increasing the effective speed of executing a loop containing a branch instruction by scanning the predecoded bits in establishing a link between successive instructions.
摘要翻译： 用于在流水线处理器中提供复杂指令的早期解码的系统和技术使用编程逻辑阵列来对指令段进行解码，并将指令位和相关联的预解码位加载到FIFO缓冲器中以累积多个这样的条目。 同时，操作数执行管道根据需要从FIFO缓冲器检索这些条目，使用预解码指令位以由指令本身确定的速率快速解码和执行指令。 由于高速缓存未命中的延迟基本上或完全被屏蔽，因为除了在高速缓存未命中之外，指令和相关联的预解码位被加载到FIFO缓冲器中比它们从其中检索得更快。 描述了一种用于增加执行三操作数构造的有效速度的方法。 公开了一种用于通过在建立连续指令之间的链接的情况下扫描预解码比特来增加执行包含分支指令的循环的有效速度的方法。
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公开(公告)号：US4594660A
公开(公告)日：1986-06-10
申请号：US434129
申请日：1982-10-13
CPC分类号： G06F9/3885 , G06F9/3863
摘要： A collector for the results of a pipelined central processing unit of a digital data processing system. The processor has a plurality of execution units, with each execution unit executing a different set of instructions of the instruction repertoire of the processor. The execution units execute instructions issued to them in order of issuance by the pipeline and in parallel. As instructions are issued to the execution units, the operation code identifying each instruction is also issued in program order to an instruction execution queue of the collector. The results of the execution of each instruction by an execution unit are stored in a result stack associated with each execution unit. Collector control causes the results of the execution of instructions to program visible registers to be stored in a master safe store register in program order which is determined by the order of instructions stored in the instruction execution stack on a first-in, first-out basis. The collector also issues write commands to write results of the execution of instructions into memory in program order.
摘要翻译： 用于数字数据处理系统的流水线中央处理单元的结果的收集器。 处理器具有多个执行单元，每个执行单元执行处理器的指令集的不同指令集。 执行单元按照管道发布的顺序执行发给他们的指令并行执行。 当向执行单元发出指令时，识别每条指令的操作代码也以程序顺序发布到收集器的指令执行队列。 由执行单元执行每条指令的结果存储在与每个执行单元相关联的结果堆栈中。 收集器控制导致执行指令的结果将可见寄存器编程存储在主安全存储寄存器中，程序顺序由存储在指令执行堆栈中的指令顺序以先进先出为基础确定 。 收集器还发出写入命令，以按程序顺序将指令的执行结果写入存储器。
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公开(公告)号：US4538237A
公开(公告)日：1985-08-27
申请号：US458795
申请日：1983-01-18
申请人： Joseph C. Circello
发明人： Joseph C. Circello
CPC分类号： G06F7/727
摘要： Method and apparatus for calculating the residue of a binary number of "n" bits with respect to a given check base m where m=2.sup.b -1. The binary number is partitioned into segments, each of b bits starting with the least significant bit. If n is not an even multiple of b, higher order bit positions of the segment containing the most significant bit of the number are filled with logical zeros. The segments are applied to levels of carry save adders to reduce the segments of the binary number to a single sum segment of b bits and a single rotated carry segment of b bits where a rotated carry segment is a carry segment produced by a carry save adder, the most significant bit of which is rotated so that it becomes the least significant bit of the rotated carry segment. Carry segments produced by carry save adders of one level are converted to rotated carry segments before being applied to a carry save adder of a lower level carry save adder. The single sum segment and single rotated carry segment produced by the lowest level carry save adder are applied to a 1's complement full adder. The b bit output of the 1's complement full adder is the residue of the binary number with respect to the check base (2.sup.b -1).
摘要翻译： 用于计算二进制数“n”位相对于m = 2b-1的给定检验基m的方法和装置。 二进制数被划分成段，每个b位以最低有效位开始。 如果n不是b的偶数倍，则包含该数字的最高有效位的段的高位位置被填充有逻辑0。 这些段被应用于进位存储加法器的电平以将二进制数的段减少到b位的单个和段和b位的单个旋转进位段，其中旋转的进位段是由进位保存加法器产生的进位段 ，其最高有效位被旋转，使其成为旋转进位段的最低有效位。 由一个级别的进位保存加法器产生的进位段在应用于较低级进位保存加法器的进位保存加法器之前被转换为旋转进位段。 由最低电平进位保存加法器产生的单个和段和单个旋转进位段应用于1的补码全加器。 1的补码全加器的b位输出是相对于检验基（2b-1）的二进制数的残差。
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48.发明授权Method and apparatus for initiating the execution of instructions using a central pipeline execution unit 失效用于使用中央流水线执行单元发起指令执行的方法和装置
公开(公告)号：US4471432A
公开(公告)日：1984-09-11
申请号：US434196
申请日：1982-10-13
申请人： John E. Wilhite , William A. Shelly , Russell W. Guenthner , Leonard G. Trubisky , Joseph C. Circello
发明人： John E. Wilhite , William A. Shelly , Russell W. Guenthner , Leonard G. Trubisky , Joseph C. Circello
CPC分类号： G06F9/3867
摘要： A method and a central execution pipeline unit for initiating the execution of instructions of a synchronous central processor unit (CPU) of a general-purpose digital data processing system. Instructions containing address information and an instruction field are obtained in program order from an instruction fetch unit of the CPU. In a first stage, requiring one clock period, the address information of an instruction is utilized to form the carrys and sums of an effective address and to initiate the formation of a virtual address. Concurrently, the instruction field is decoded to produce memory command signals and data alignment signals. In a second stage, the formation of the effective and virtual addresses initiated in the first stage is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU. Also during the second stage, memory command signals are sent to the cache unit and the instruction field is converted to an execution code for one of a plurality of execution units, and the execution unit to execute the code is designated. In a third stage, the virtual address is converted to a physical address, or real page number, which is transmitted to the cache unit. The execution code is sent to the designated execution unit; however, if the execution unit is the central unit, the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. In the fourth stage, data alignment control signals are sent to a distributor of the central execution pipeline unit.
摘要翻译： 一种用于启动通用数字数据处理系统的同步中央处理器单元（CPU）的指令执行的方法和中央执行流水线单元。 从CPU的指令提取单元以程序顺序获取包含地址信息和指令字段的指令。 在需要一个时钟周期的第一阶段中，使用指令的地址信息来形成有效地址的进位和和并且启动虚拟地址的形成。 同时，指令字段被解码以产生存储器命令信号和数据对准信号。 在第二阶段中，完成在第一阶段中发起的有效和虚拟地址的形成，虚拟地址的字地址部分被发送到CPU的高速缓存单元。 此外，在第二阶段期间，存储器命令信号被发送到高速缓存单元，并且指令字段被转换为多个执行单元之一的执行代码，并且指定执行代码执行代码。 在第三阶段中，将虚拟地址转换为物理地址或实际页号，该地址被发送到高速缓存单元。 执行代码被发送到指定的执行单元; 然而，如果执行单元是中央单元，则执行单元是中央单元，该单元的执行代码被转换为执行单元控制信号。 在第四阶段，将数据对准控制信号发送到中央执行流水线单元的分配器。
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49.发明申请公开(公告)号：US20160173282A1
公开(公告)日：2016-06-16
申请号：US14570611
申请日：2014-12-15
CPC分类号： H04L9/0894 , H04L9/0822 , H04L2209/12
摘要： Methods and systems are disclosed for key management for on-the-fly hardware decryption within an integrated circuit. Encrypted information is received from an external memory and stored in an input buffer within the integrated circuit. The encrypted information includes one or more encrypted key blobs. The encrypted key blobs include one or more secret keys for encrypted code associated with one or more encrypted software images stored within the external memory. A key-encryption key (KEK) code for the encrypted key blobs is received from an internal data storage medium within the integrated circuit, and the KEK code is used to generate one or more key-encryption keys (KEKs). A decryption system then decrypts the encrypted key blobs using the KEKs to obtain the secret keys, and the decryption system decrypts the encrypted code using the secret keys. The resulting decrypted software code is then available for further processing.
摘要翻译： 公开了用于集成电路内的即时硬件解密的密钥管理的方法和系统。 从外部存储器接收加密信息并存储在集成电路内的输入缓冲器中。 加密的信息包括一个或多个加密的密钥块。 加密的密钥块包括用于与存储在外部存储器中的一个或多个加密软件图像相关联的加密代码的一个或多个秘密密钥。 从集成电路内的内部数据存储介质接收加密密钥块的密钥加密密钥（KEK）代码，并且使用KEK码生成一个或多个密钥加密密钥（KEK）。 然后，解密系统使用KEK解密加密的密钥块以获得秘密密钥，并且解密系统使用密钥对加密的密码进行解密。 所得到的解密的软件代码然后可用于进一步处理。
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公开(公告)号：US08566672B2
公开(公告)日：2013-10-22
申请号：US13053962
申请日：2011-03-22
IPC分类号： G11C29/00
CPC分类号： G06F11/1016 , G11C29/52 , G11C2029/0411
摘要： Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the data and, in response to a read access at the memory address, are employed to check for errors in both the address and the data provided in response to the read access (the read data). The ECC checkbit generation process can result, for particular memory addresses, in checkbits that can incorrectly indicate whether errors are present in the read data. Accordingly, the checkbits can be selectively inverted based on the memory address so that the checkbit pattern will not result in an incorrect error detection or correction.
摘要翻译： 基于要写入的数据（写入数据）和存储器地址的每次对存储器地址的写入生成纠错码（ECC）校验码。 ECC校验位与数据一起存储，并且响应于在存储器地址处的读取访问来检查响应于读取访问（读取数据）提供的地址和数据中的错误。 对于特定的存储器地址，ECC校验位生成过程可能导致错误地指示读取数据中是否存在错误的校验位。 因此，可以基于存储器地址选择性地反转校验位，使得校验位模式不会导致不正确的错误检测或校正。
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