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41.发明授权High efficiency power amplifier having reduced output matching networks for use in portable devices 有权具有减少的用于便携式设备的输出匹配网络的高效率功率放大器公开(公告)号：US06262629B1
公开(公告)日：2001-07-17
申请号：US09347675
申请日：1999-07-06
IPC分类号： H03F368
CPC分类号： H03F1/0288 , H03F1/0261 , H03F2200/198
摘要： A power amplifier includes a carrier amplifier path and a peaking amplifier path. The carrier amplifier path includes a carrier amplifier (208), and an impedance transforming network (214). The peaking amplifier path includes a peaking amplifier (210), an impedance transforming network (216), and a phase delay quarter wave element (226). The arrangement forms an inverted Doherty combiner where as the nominal impedance at a summing node (230) increases with increased conduction from the peaking amplifier, the load impedance at the output of the carrier amplifier decreases so as to maintain the carrier amplifier at a saturation point as the input signal (232) increases, and results in a reduction of the number of phase delay elements needed over a conventional Doherty approach. In a preferred embodiment the carrier and peaking amplifiers consist of cascaded stages, and are disposed on a common integrated circuit die (304). The impedance transforming networks and phase delay element are disposed on a common substrate (306), as is an input splitter network (308).
摘要翻译： 功率放大器包括载波放大器路径和峰化放大器路径。 载波放大器路径包括载波放大器（208）和阻抗变换网络（214）。 峰化放大器路径包括峰值放大器（210），阻抗变换网络（216）和相位延迟四分之一波长元件（226）。 该布置形成反向Doherty组合器，其中当加法节点（230）处的标称阻抗随着来自峰化放大器的传导增加而增加时，载波放大器的输出处的负载阻抗减小，以便将载波放大器保持在饱和点 随着输入信号（232）增加，并且导致相对于常规Doherty方法所需的相位延迟元件的数量的减少。 在优选实施例中，载波和峰值放大器由级联级组成，并且被布置在公共集成电路管芯（304）上。 阻抗变换网络和相位延迟元件如输入分配器网络（308）一样设置在公共基板（306）上。
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公开(公告)号：US5898912A
公开(公告)日：1999-04-27
申请号：US673857
申请日：1996-07-01
申请人： Joseph P. Heck , Robert E. Stengel
发明人： Joseph P. Heck , Robert E. Stengel
CPC分类号： H04L25/063 , H03D3/008 , H03G3/3052
摘要： A receiver (300) includes input (I.sub.in), output (V.sub.out), forward path with filter (104, and 108), and feedback path with error amplifier (112) coupled into the forward path. Coupled to the feedback path is an error signal storage device (408, 508). A control circuit (320) responsive to input signal amplitude couples to the storage device (408, 508) and retrieves stored error signal information for use by the feedback path. During calibration, a forward path stage is stimulated with a plurality of signals of known amplitude to generate outputs (V.sub.out). The outputs are compared to a reference to generate error signals. Error signal values are stored in memory as a function of input signal amplitude. A plurality of error signal values are stored. During operation, stage input signals are detected and compared with the plurality of signals of known amplitude. Upon detection of a match, the error signal value associated with the signal of interest is retrieved from memory and employed during DC offset compensation.
摘要翻译： 接收器（300）包括输入（Iin），输出（Vout），具有滤波器（104和108）的前向路径以及耦合到前向路径中的误差放大器（112）的反馈路径。 耦合到反馈路径的是误差信号存储装置（408,508）。 响应于输入信号幅度的控制电路（320）耦合到存储设备（408,508），并且检索所存储的误差信号以供反馈路径使用。 在校准期间，通过已知幅度的多个信号刺激正向路径级以产生输出（Vout）。 将输出与参考值进行比较以产生误差信号。 误差信号值作为输入信号幅度的函数存储在存储器中。 存储多个误差信号值。 在操作期间，检测舞台输入信号并与已知幅度的多个信号进行比较。 在检测到匹配时，从存储器检索与感兴趣的信号相关联的误差信号值，并在DC偏移补偿期间采用。
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43.发明授权Receiver sensitivity threshold extended with the combination of an unmodulated signal with the received signal 失效接收机灵敏度阈值与未调制信号与接收信号的组合扩展
公开(公告)号：US5303411A
公开(公告)日：1994-04-12
申请号：US883820
申请日：1992-05-11
申请人： Robert E. Stengel , Paul D. Marko
发明人： Robert E. Stengel , Paul D. Marko
IPC分类号： H04B1/10
CPC分类号： H04B1/10
摘要： A receiver (10) is provided where an information signal (11) is received (12) and examined to determine (20) its signal strength. When the signal strength is at least equal to a threshold, an unmodulated signal (40) is added to the received signal to improve the sensitivity of the receiver.
摘要翻译： 提供接收机（10），其中接收信息信号（11）（12）并进行检查以确定（20）其信号强度。 当信号强度至少等于阈值时，将未调制信号（40）加到接收信号上以提高接收机的灵敏度。
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公开(公告)号：US5166857A
公开(公告)日：1992-11-24
申请号：US812927
申请日：1991-12-24
摘要： An integrated switch (100) includes a first input port (102), a second input port (112) and an output port (106). The integrated switch (100) comprises a first electronically-tunable integrated capacitor (104) having a control line (108) for selectively coupling the first input port (102) to the output port (106). The switch (100) also includes a second electronically-tunable integrated capacitor (110) having a control line (108) for selectively coupling the second input port (112) to the output port (106).
摘要翻译： 集成开关（100）包括第一输入端口（102），第二输入端口（112）和输出端口（106）。 集成开关（100）包括具有用于选择性地将第一输入端口（102）耦合到输出端口（106）的控制线（108）的第一电子可调谐集成电容器（104）。 开关（100）还包括具有用于选择性地将第二输入端口（112）耦合到输出端口（106）的控制线（108）的第二电子可调谐集成电容器（110）。
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公开(公告)号：US5151709A
公开(公告)日：1992-09-29
申请号：US419551
申请日：1989-10-10
申请人： Quirino Balzano , Robert E. Stengel
发明人： Quirino Balzano , Robert E. Stengel
摘要： An antenna (10) capable of receiving signals of various frequencies includes a series of superconducting antenna segments and decouplers disposed between each adjacent pair of antenna segments for selectively decoupling at least one antenna segment from the antenna (10) in response to the frequency of the signal received.
摘要翻译： 能够接收各种频率的信号的天线（10）包括一系列超导天线段和设置在每个相邻天线段对之间的去耦器，用于响应于所述天线（10）的频率选择性地将天线段与天线（10）分离 收到信号。
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公开(公告)号：US4785263A
公开(公告)日：1988-11-15
申请号：US55207
申请日：1987-05-28
CPC分类号： H03B5/1228 , H03B5/1203 , H03B5/1243 , H03B2200/0008 , H03B2200/0032
摘要： A Ga As FET oscillator includes an FET having gate-drain and source connections. A tuned circuit is connected to the FET gate. Bias voltage is supplied to the FET. A parallel-connected resistor and capacitor is connected to the FET source. A Schottky diode is connected across the FET gate-source junction and the parallel connected resistor and capacitor, with its anode connected to the FET gate and its cathode connected to the resistor and capacitor. The Schottky diode limits the positive voltage across the gate-source junction of the Ga As FET to prevent gate-source current flow.
摘要翻译： GaAs FET振荡器包括具有栅极 - 漏极和源极连接的FET。 调谐电路连接到FET门。 偏置电压被提供给FET。 并联电阻和电容连接到FET源。 肖特基二极管连接在FET栅极 - 源极结和并联的电阻和电容之间，其阳极连接到FET栅极，其阴极连接到电阻和电容。 肖特基二极管限制Ga As FET栅极 - 源极结两端的正电压，以防止栅极 - 源极电流流动。
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47.发明申请METHOD AND APPARATUS FOR A MULTI-ANTENNA DEVICE THAT USES A SINGLE BASEBAND FILTER AND ANALOG-TO-DIGITAL CONVERTER 有权使用单个基带滤波器和模拟数字转换器的多天线设备的方法和装置公开(公告)号：US20130114588A1
公开(公告)日：2013-05-09
申请号：US13288212
申请日：2011-11-03
CPC分类号： H04B1/0064 , H04B7/0837
摘要： A multi-antenna device (200) comprising a set of antennas (210-214), a set of receivers (220-224), a multiplexer (270), a baseband filter (242), an analog-to-digital converter (244), and a de-multiplexer (272). The receivers (220-224) can be linked to the antennas (210-214) in a one-to-one manner. The multiplexer (270) can generate a composite analog signal from a set of different analog signals, one received from different ones of the antennas (210-214). The baseband filter (242) can filter the composite analog signal. The analog-to-digital converter (244) can convert the composite analog signal after being filtered by the baseband filter into a composite digital signal. The de-multiplexer (272) can generate a set of different digital signals from the composite digital signal. Each of the different digital signals can correspond to one of the different analog signals in a one-to-one manner.
摘要翻译： 一种多天线设备（200），包括一组天线（210-214），一组接收机（220-224），多路复用器（270），基带滤波器（242），模数转换器 244）和解复用器（272）。 接收器（220-224）可以以一对一的方式链接到天线（210-214）。 多路复用器（270）可以从一组不同的模拟信号中产生一个复合模拟信号，一组从不同的天线（210-214）接收。 基带滤波器（242）可以对复合模拟信号进行滤波。 模数转换器（244）可以将由基带滤波器滤波后的复合模拟信号转换为复合数字信号。 解复用器（272）可以从复合数字信号产生一组不同的数字信号。 每个不同的数字信号可以以一对一的方式对应于不同的模拟信号之一。
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公开(公告)号：US07957715B2
公开(公告)日：2011-06-07
申请号：US12121102
申请日：2008-05-15
申请人： Robert E. Stengel
发明人： Robert E. Stengel
IPC分类号： H04B1/26
CPC分类号： H04B1/1638
摘要： A method and frequency converter for a radio rapid frequency signal scanning and including a local oscillator signal synthesis source (112) producing a local oscillator signal (502) with local oscillator bursts (210). The local oscillator bursts (210) contain pulse width modulated RF frequency pulses (602). Each local oscillator burst having, for a pre-determined duration, RF frequency pulses within an effective amplitude above a pre-determined threshold (260). Each local oscillator burst (210) having also has effective amplitude pulse shaping envelope (504) that reduces at least one frequency domain component magnitude (310) of the local oscillator signal (300). A radio frequency mixer (110) receives an RF signal input (104) and the local oscillator signal to produce an output signal (160) at a frequency related to a combination of a frequency of the RF signal input and a frequency of the local oscillator signal.
摘要翻译： 一种用于无线电快速频率信号扫描的方法和频率转换器，并且包括用本地振荡器脉冲串（210）产生本地振荡器信号（502）的本地振荡器信号合成源（112）。 本地振荡器脉冲串（210）包含脉冲宽度调制的RF频率脉冲（602）。 对于预定的持续时间，每个本地振荡器突发具有高于预定阈值（260）的有效幅度内的RF频率脉冲。 每个本地振荡器突发（210）也具有降低本地振荡器信号（300）的至少一个频域分量幅度（310）的有效幅度脉冲整形包络（504）。 射频混频器（110）接收RF信号输入（104）和本地振荡器信号以产生与RF信号输入的频率和本地振荡器的频率的组合相关的频率的输出信号（160） 信号。
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49.发明申请公开(公告)号：US20080095291A1
公开(公告)日：2008-04-24
申请号：US11584410
申请日：2006-10-19
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H04L7/0012
摘要： A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measurement of the clock frequency of the received digital signal. The coarse and fine measurements are used to calculate a value for programming a direct digital synthesizer to produce a clock signal that is an approximate replica of the clock frequency of the received digital signal.
摘要翻译： 公开了用于编程直接数字合成器的时钟数据恢复的系统和方法。 计数器用于计算接收到的数字信号的时钟频率的粗略测量，采用分接延迟线来计算接收的数字信号的时钟频率的精细测量。 粗略和精细的测量用于计算用于编程直接数字合成器的值以产生作为接收的数字信号的时钟频率的近似副本的时钟信号。
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公开(公告)号：US07109766B2
公开(公告)日：2006-09-19
申请号：US10830337
申请日：2004-04-22
申请人： Jeffrey B. White , Joseph A. Charaska , Manuel P. Gabato, Jr. , Paul H. Gailus , Robert E. Stengel
发明人： Jeffrey B. White , Joseph A. Charaska , Manuel P. Gabato, Jr. , Paul H. Gailus , Robert E. Stengel
IPC分类号： H03L7/08
CPC分类号： H03L7/16 , H03K5/133 , H03K2005/00026 , H03K2005/00058 , H03L7/0812
摘要： A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.
摘要翻译： 延迟锁定环路300，其包括：用于产生具有可调频率的时钟信号（322）的可调频率源（320） 调整和抽头选择控制器（310），用于根据第二频率确定第一频率，并使频率源将时钟信号的频率调整到基本上第一频率;第二频率是期望的频率 第一输出信号; 延迟线（330），被配置为接收用于产生多个相移时钟信号的时钟信号; 以及第一选择电路（370），用于接收多个相移时钟信号，并用于在调整和分接选择控制器的控制下一次一个地选择第一个相移时钟信号序列，用于产生 第一输出信号具有基本上第二频率。
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