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公开(公告)号：US20060238528A1
公开(公告)日：2006-10-26
申请号：US11384101
申请日：2006-03-17
IPC分类号： G09G5/00
CPC分类号： G09G3/22 , G09G3/2014 , G09G2310/0254 , G09G2310/027 , G09G2330/021
摘要： A driving apparatus and a driving method for an electron emission device include a polarity operator for receiving an external video data signal and a horizontal synchronization signal, and generating a polarity control signal in response to the horizontal synchronization signal. The apparatus further includes a data inverter for selectively inverting video data output from the polarity operator, a serial-parallel converter for converting video data output from the data inverter into parallel data, a pulse width modulator for modulating a pulse width of the parallel data output from the serial-parallel converter, and a polarity controller for selectively inverting a signal output from the pulse width modulator.
摘要翻译： 电子发射装置的驱动装置和驱动方法包括用于接收外部视频数据信号和水平同步信号的极性运算器，并且响应于水平同步信号产生极性控制信号。 该装置还包括用于选择性地反转从极性运算器输出的视频数据的数据反相器，将从数据反相器输出的视频数据转换成并行数据的串并联转换器，用于调制并行数据输出的脉冲宽度的脉宽调制器 串行并行转换器和用于选择性地反相从脉冲宽度调制器输出的信号的极性控制器。
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42.发明申请Semiconductor memory devices including a vertical channel transistor and methods of manufacturing the same 有权包括垂直沟道晶体管的半导体存储器件及其制造方法公开(公告)号：US20060097304A1
公开(公告)日：2006-05-11
申请号：US11151673
申请日：2005-06-13
申请人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
发明人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
摘要翻译： 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。
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公开(公告)号：US20060017104A1
公开(公告)日：2006-01-26
申请号：US11183997
申请日：2005-07-19
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
CPC分类号： H01L29/78696 , H01L29/66666 , H01L29/66772 , H01L29/78642
摘要： A semiconductor device may include a tubular channel pattern vertically extending from a semiconductor substrate. A gate insulation layer may be provided on faces exposed through the channel pattern. A gate electrode may be provided on the gate insulation layer. The gate electrode may fill the channel pattern. A conductive region, which may serve as lower source/drain regions, may be formed at a surface portion of the semiconductor substrate. The conductive region may contact a lower portion of the channel pattern. A conductive pattern, which may serve as upper source/drain regions, may horizontally extend from an upper portion of the channel pattern.
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44.发明申请METHOD OF FORMING SEMICONDUCTOR DEVICES WITH BURIED GATE ELECTRODES AND DEVICES FORMED BY THE SAME 审中-公开用铜基电极形成半导体器件的方法及其形成的器件公开(公告)号：US20120273791A1
公开(公告)日：2012-11-01
申请号：US13546296
申请日：2012-07-11
申请人： Bongsoo Kim , Chul Lee , Deoksung Hwang , Sang-Bin Ahn
发明人： Bongsoo Kim , Chul Lee , Deoksung Hwang , Sang-Bin Ahn
IPC分类号： H01L29/78
CPC分类号： H01L29/4236 , H01L21/823437 , H01L29/66621 , H01L29/78
摘要： A polycrystalline semiconductor layer is formed on a cell active region and a peripheral active region of a substrate. A buried gate electrode is formed in the substrate in the cell active region at a level below the polycrystalline semiconductor layer after forming the polycrystalline semiconductor layer. A gate electrode is formed on the substrate in the peripheral active region from the polysilicon semiconductor layer after forming the buried gate electrode.
摘要翻译： 多晶半导体层形成在基板的单元有源区和周边有源区上。 在形成多晶半导体层之后，在多晶半导体层下方的电池有源区的基板中形成埋入栅电极。 在形成掩埋栅电极之后，在多晶硅半导体层的外围有源区的基板上形成栅电极。
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公开(公告)号：USD637573S1
公开(公告)日：2011-05-10
申请号：US29378286
申请日：2010-11-02
申请人： Chul Lee , Myung Whoon Lee , Jong Chul Kim
设计人： Chul Lee , Myung Whoon Lee , Jong Chul Kim
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47.发明授权Methods of manufacturing semiconductor memory devices including a vertical channel transistor 有权制造包括垂直沟道晶体管的半导体存储器件的方法公开(公告)号：US07531412B2
公开(公告)日：2009-05-12
申请号：US11151673
申请日：2005-06-13
申请人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
发明人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
摘要翻译： 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。
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48.发明申请DRAM devices including fin transistors and methods of operating the DRAM devices 审中-公开包括鳍式晶体管的DRAM器件和操作DRAM器件的方法公开(公告)号：US20080084731A1
公开(公告)日：2008-04-10
申请号：US11896029
申请日：2007-08-29
申请人： Chul Lee , Dong-Gun Park , Woun-Suck Yang , Makoto Yoshida
发明人： Chul Lee , Dong-Gun Park , Woun-Suck Yang , Makoto Yoshida
IPC分类号： G11C11/401 , H01L27/108
CPC分类号： G11C11/404 , G11C11/4076 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L27/10894 , H01L29/7851
摘要： A dynamic random access memory (DRAM) device may include: a semiconductor substrate including an active fin, an active region, and an isolation layer; one or more cell gate structures on a central portion of the active fin; one or more dummy gate structures on a peripheral portion of the active fin; one or more source/drain regions at an upper portion of the active fin adjacent to the one or more cell gate structures; a first insulating interlayer on the semiconductor substrate; a bit line structure electrically connected to the at least one source region; a second insulating interlayer on the first insulating interlayer; one or more capacitors electrically connected to the at least one drain region; a third insulating interlayer on the second insulating interlayer; and a wire connected to the active region and at least one of the one or more dummy gate structures.
摘要翻译： 动态随机存取存储器（DRAM）装置可以包括：半导体衬底，其包括有源鳍片，有源区域和隔离层; 有源鳍片的中心部分上的一个或多个单元栅极结构; 活动鳍片的周边部分上的一个或多个虚拟栅极结构; 在与所述一个或多个单元栅极结构相邻的所述有源鳍片的上部处的一个或多个源极/漏极区域; 半导体衬底上的第一绝缘中间层; 电连接到所述至少一个源极区的位线结构; 在所述第一绝缘中间层上的第二绝缘中间层; 电连接到所述至少一个漏极区的一个或多个电容器; 在所述第二绝缘中间层上的第三绝缘中间层; 以及连接到有源区域和所述一个或多个虚拟栅极结构中的至少一个的导线。
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公开(公告)号：US20070152553A1
公开(公告)日：2007-07-05
申请号：US11639432
申请日：2006-12-15
CPC分类号： H05K7/20963 , H01J2217/492
摘要： A plasma display panel adapted to minimize noise/vibration as well as a heat generated therefrom. In the plasma display panel, a display panel displays a picture while a porous pad is provided behind the display panel to prevent the transfer of noise/vibration to an associated heat proof panel. When the PDP is mounted within a case, a second porous pad can be provided on an inner surface of the case opposite the display panel and adjacent to an associated printed circuit board for additional noise/vibration damping.
摘要翻译： 等离子体显示面板适于最小化噪音/振动以及由此产生的热量。 在等离子体显示面板中，显示面板显示图像，同时在显示面板后面设置多孔垫以防止噪声/振动传递到相关的防热面板。 当PDP安装在壳体内时，第二多孔垫可以设置在与显示面板相对的壳体的内表面上并且邻近相关的印刷电路板，用于额外的噪声/振动阻尼。
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50.发明申请HYDROTHERMALLY STABLE MICROPOROUS MOLECULAR SIEVE CATALYST AND PREPARATION METHOD THEREOF 有权水热稳定型微波分子筛催化剂及其制备方法公开(公告)号：US20070082809A1
公开(公告)日：2007-04-12
申请号：US11427001
申请日：2006-06-28
申请人： Sun Choi , Yong Kim , Deuk Park , Suk Kim , Il Yang , Hee Kim , Yong Park , Chul Lee , Won Choi , Kwang Ko , Na Kang
发明人： Sun Choi , Yong Kim , Deuk Park , Suk Kim , Il Yang , Hee Kim , Yong Park , Chul Lee , Won Choi , Kwang Ko , Na Kang
IPC分类号： B01J27/182 , B01J29/08 , B01J29/18 , B01J29/00 , B01J29/04
CPC分类号： B01J29/40 , B01J29/061 , B01J29/405 , B01J29/46 , B01J2229/12 , B01J2229/18 , C10G29/205 , C10G2400/20
摘要： Disclosed are a hydrothermally stable porous molecular sieve catalyst and a preparation method thereof. The catalyst consists of a product obtained by the evaporation of water from a raw material mixture comprising a molecular sieve having a framework of Si—OH—Al—, a water-insoluble metal salt and a phosphate compound. The catalyst maintains its physical and chemical stabilities even in an atmosphere of high temperature and humidity. Accordingly, the catalyst shows excellent catalytic activity even when it is used in a severe process environment of high temperature and humidity in heterogeneous catalytic reactions, such as various oxidation/reduction reactions, including catalytic cracking reactions, isomerization reactions, alkylation reactions and esterification reactions.
摘要翻译： 公开了一种水热稳定的多孔分子筛催化剂及其制备方法。 催化剂由通过从包含具有Si-OH-Al-骨架的分子筛，水不溶性金属盐和磷酸盐化合物的原料混合物中蒸发水得到的产物组成。 即使在高温和高湿的气氛下，催化剂仍保持其物理和化学稳定性。 因此，即使在非均相催化反应如催化裂化反应，异构化反应，烷基化反应，酯化反应等各种氧化/还原反应中，在恶劣的高温高湿环境下使用，催化剂也具有优异的催化活性。
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