公开(公告)号：US20070138551A1

公开(公告)日：2007-06-21

申请号：US11637704

申请日：2006-12-13

Applicant: Kwang Ko

Inventor： Kwang Ko

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/7835 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66613 ,  H01L29/66659

Abstract: There is provided a high voltage semiconductor device comprising: a semiconductor substrate of a first conductivity type, including a first region, a second region relatively lower than the first region, and a sloped region between the first region and the second region; a drift region of a second conductivity type, formed on the second region; a source region of the second conductivity type, disposed on the first region, and spaced apart from the drift region by the sloped region; a drain region of the second conductivity type, disposed on the drift region; a field plate positioned on the drift region in the second region; a gate insulating layer disposed between the source region and the drift region; and a gate electrode layer, which is disposed on the gate insulating layer and extends to above the field plate.

Abstract translation: 提供了一种高电压半导体器件，包括：第一导电类型的半导体衬底，包括第一区域，相对低于第一区域的第二区域和第一区域与第二区域之间的倾斜区域; 形成在第二区域上的第二导电类型的漂移区; 所述第二导电类型的源极区域设置在所述第一区域上，并且通过所述倾斜区域与所述漂移区域间隔开; 位于漂移区上的第二导电类型的漏极区; 位于所述第二区域中的所述漂移区上的场板; 设置在所述源极区域和所述漂移区域之间的栅极绝缘层; 以及栅极电极层，其设置在栅极绝缘层上并延伸到场板的上方。

公开(公告)号：US20070010699A1

公开(公告)日：2007-01-11

申请号：US11426847

申请日：2006-06-27

Applicant: Sun Choi ,  Yong Kim ,  Deuk Park ,  Suk Kim ,  Il Yang ,  Hee Kim ,  Yong Park ,  Chul Lee ,  Won Choi ,  Kwang Ko ,  Na Kang

Inventor： Sun Choi ,  Yong Kim ,  Deuk Park ,  Suk Kim ,  Il Yang ,  Hee Kim ,  Yong Park ,  Chul Lee ,  Won Choi ,  Kwang Ko ,  Na Kang

IPC: C07C4/02

CPC classification number: C07C4/06 ,  C10G2400/20 ,  C07C11/02

Abstract: Disclosed is a process for producing light olefins from hydrocarbon feedstock. The process is characterized in that a porous molecular sieve catalyst consisting of a product obtained by evaporating water from a raw material mixture comprising a molecular sieve with a framework of Si—OH—Al— groups, a water-insoluble metal salt, and a phosphate compound, is used to produce light olefins, particularly ethylene and propylene, from hydrocarbon, while maintaining excellent selectivity to light olefins. According to the process, by the use of a specific catalyst with hydrothermal stability, light olefins can be selectively produced in high yield with high selectivity from hydrocarbon feedstock, particularly full-range naphtha. In particular, the process can maintain higher cracking activity than the reaction temperature required in the prior thermal cracking process for the production of light olefins, and thus, can produce light olefins with high selectivity and conversion from hydrocarbon feedstock.

Abstract translation: 公开了一种从烃原料生产轻质烯烃的方法。 该方法的特征在于，由通过从包含具有Si-OH-Al-基团的骨架的分子筛，水不溶性金属盐和磷酸盐的原料混合物蒸发水而获得的产物的多孔分子筛催化剂 化合物，用于从烃生产轻质烯烃，特别是乙烯和丙烯，同时保持对轻质烯烃的优异选择性。 根据该方法，通过使用具有水热稳定性的特定催化剂，可以从烃原料，特别是全范围石脑油以高选择性高选择性地制备轻质烯烃。 特别地，该方法可以保持比用于生产轻质烯烃的现有热裂解方法中所需的反应温度更高的裂化活性，因此可以从烃原料生产具有高选择性和转化率的轻质烯烃。

公开(公告)号：US20070152245A1

公开(公告)日：2007-07-05

申请号：US11646837

申请日：2006-12-27

Applicant: Kwang Ko

Inventor： Kwang Ko

IPC: H01L29/76

CPC classification number: H01L29/66621 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/7834

Abstract: Disclosed is a semiconductor device. The semiconductor device includes; a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on both sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.

Abstract translation: 公开了一种半导体器件。 半导体器件包括： 形成在半导体衬底中的一对漂移区; 形成在所述一对漂移区域之间的沟槽区域; 在所述沟槽区域的两个侧壁上的氧化物层间隔物; 形成在沟槽区域中的栅极; 以及分别形成在该对漂移区域中的源极和漏极。

公开(公告)号：US20070060042A1

公开(公告)日：2007-03-15

申请号：US11468718

申请日：2006-08-30

Applicant: Kwang Ko

Inventor： Kwang Ko

IPC: H04H1/00

CPC classification number: H04H20/38 ,  H04H60/51 ,  H04L65/1016 ,  H04L65/4076

Abstract: A system for providing an interactive broadcast service and method thereof are disclosed, by which a communication service and an interactive broadcast service can be unitedly supported in an IMS (Internet protocol Multimedia Subsystem) environment. The present invention includes a first server receiving a message of the protocol from the UE and making a registration for a service subscription for the UE from subscription-related information included in the message, a first media server receiving a multimedia stream of the broadcast service to be transmitted to the registered UE from a corresponding broadcasting network, and a second media server connected to the broadcasting network, converting interaction data inserted in the message of the protocol received from the UE to a signal format supported by the broadcasting network.

Abstract translation: 公开了一种用于提供交互式广播服务的系统及其方法，通过该系统可以在IMS（因特网协议多媒体子系统）环境中统一支持通信服务和交互式广播服务。 本发明包括第一服务器，接收来自UE的协议消息，并从包括在消息中的订阅相关信息进行用于UE的服务订阅的注册，第一媒体服务器将广播服务的多媒体流接收到 从相应的广播网络发送到注册的UE，以及连接到广播网络的第二媒体服务器，将从UE接收的协议的消息中插入的交互数据转换成由广播网络支持的信号格式。

公开(公告)号：US20060138584A1

公开(公告)日：2006-06-29

申请号：US11318441

申请日：2005-12-28

Applicant: Kwang Ko

Inventor： Kwang Ko

IPC: H01L29/00

CPC classification number: H01L21/823462 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7835

Abstract: A semiconductor device includes a substrate including a high-voltage transistor area provided with a high-voltage transistor and a low-voltage transistor area provided with a low-voltage transistor; a LOCOS layer provided as a device isolation layer of the high-voltage transistor area; and a shallow-trench isolation layer provided as a device isolation layer of the low-voltage transistor area. Accordingly, a sufficient breakdown voltage level can be provided in a high-voltage transistor area, on-resistance and leakage current can be enhanced, and the chip area in a low-voltage transistor area can be reduced.

Abstract translation: 半导体器件包括：衬底，其包括设置有高压晶体管的高压晶体管区域和设置有低压晶体管的低压晶体管区域; 提供作为高压晶体管区域的器件隔离层的LOCOS层; 以及作为低压晶体管区域的器件隔离层提供的浅沟槽隔离层。 因此，可以在高压晶体管区域提供足够的击穿电压电平，可以提高导通电阻和漏电流，并且可以降低低压晶体管区域中的芯片面积。

公开(公告)号：US20050142723A1

公开(公告)日：2005-06-30

申请号：US11022847

申请日：2004-12-28

Applicant: Kwang Ko

Inventor： Kwang Ko

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/0847 ,  H01L29/7835

Abstract: The present invention provides a method of fabricating a high-voltage CMOS device, in which an extended drain region failing to enclose a heavily-doped drain region is separated from a high current flow path to enable high electric field concentration and breakdown to occur within a bulk of a silicon substrate and by which device reliability can be enhanced. The present invention includes the steps of forming a pad oxide layer on a substrate, forming a heavily doped drain region, a heavily doped source region, a source region, and an extended drain region failing to enclose the heavily doped drain region by ion implantation using a pattern provided on the pad oxide layer, forming a field oxide layer on a prescribed area of the extended drain region, and forming a gate and a gate spacer over the substrate.

Abstract translation: 本发明提供一种制造高电压CMOS器件的方法，其中不能包围重掺杂漏极区域的扩展漏极区域与高电流流动路径分离，以使高电场浓度和击穿发生在 硅衬底的大部分，并且可以增强器件的可靠性。 本发明包括以下步骤：在衬底上形成焊盘氧化物层，形成重掺杂漏极区，重掺杂源极区，源极区和未通过离子注入包围重掺杂漏极区的延伸漏极区，使用 设置在焊盘氧化物层上的图案，在延伸漏极区域的规定区域上形成场氧化物层，以及在衬底上形成栅极和栅极间隔物。

公开(公告)号：US20050142787A1

公开(公告)日：2005-06-30

申请号：US11022655

申请日：2004-12-28

Applicant: Kwang Ko

Inventor： Kwang Ko

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8222

CPC classification number: H01L29/66272

Abstract: The present invention provides a method of fabricating a self-aligned bipolar transistor, by which the fabricating method can be simplified by forming P+ and N+ junctions by self-alignment and by which device reliability can be enhanced. The present invention includes the steps of forming a well in a substrate isolated by a device isolation layer, forming a polysilicon gate on the substrate, forming an insulating layer on the substrate, forming a sidewall spacer on lateral sides of the polysilicon gate by etching the insulating layer, forming a P+ ion implanted region in the substrate, forming an N+ ion implanted region in the substrate, and forming silicide on the P+ and N+ ion implanted regions.

Abstract translation: 本发明提供一种制造自对准双极晶体管的方法，通过该方法可以通过自对准形成P +和N +结来简化制造方法，从而可以提高器件的可靠性。 本发明包括以下步骤：在通过器件隔离层隔离的衬底中形成阱，在衬底上形成多晶硅栅极，在衬底上形成绝缘层，通过蚀刻形成在多晶硅栅极的侧面上形成侧壁间隔物 绝缘层，在衬底中形成P + +离子注入区，在衬底中形成N + +离子注入区，并在P + / SUP>和N + +离子注入区域。

公开(公告)号：US20070082809A1

公开(公告)日：2007-04-12

申请号：US11427001

申请日：2006-06-28

Applicant: Sun Choi ,  Yong Kim ,  Deuk Park ,  Suk Kim ,  Il Yang ,  Hee Kim ,  Yong Park ,  Chul Lee ,  Won Choi ,  Kwang Ko ,  Na Kang

Inventor： Sun Choi ,  Yong Kim ,  Deuk Park ,  Suk Kim ,  Il Yang ,  Hee Kim ,  Yong Park ,  Chul Lee ,  Won Choi ,  Kwang Ko ,  Na Kang

IPC: B01J27/182 ,  B01J29/08 ,  B01J29/18 ,  B01J29/00 ,  B01J29/04

CPC classification number: B01J29/40 ,  B01J29/061 ,  B01J29/405 ,  B01J29/46 ,  B01J2229/12 ,  B01J2229/18 ,  C10G29/205 ,  C10G2400/20

Abstract: Disclosed are a hydrothermally stable porous molecular sieve catalyst and a preparation method thereof. The catalyst consists of a product obtained by the evaporation of water from a raw material mixture comprising a molecular sieve having a framework of Si—OH—Al—, a water-insoluble metal salt and a phosphate compound. The catalyst maintains its physical and chemical stabilities even in an atmosphere of high temperature and humidity. Accordingly, the catalyst shows excellent catalytic activity even when it is used in a severe process environment of high temperature and humidity in heterogeneous catalytic reactions, such as various oxidation/reduction reactions, including catalytic cracking reactions, isomerization reactions, alkylation reactions and esterification reactions.

Abstract translation: 公开了一种水热稳定的多孔分子筛催化剂及其制备方法。 催化剂由通过从包含具有Si-OH-Al-骨架的分子筛，水不溶性金属盐和磷酸盐化合物的原料混合物中蒸发水得到的产物组成。 即使在高温和高湿的气氛下，催化剂仍保持其物理和化学稳定性。 因此，即使在非均相催化反应如催化裂化反应，异构化反应，烷基化反应，酯化反应等各种氧化/还原反应中，在恶劣的高温高湿环境下使用，催化剂也具有优异的催化活性。

公开(公告)号：US20060145251A1

公开(公告)日：2006-07-06

申请号：US11320485

申请日：2005-12-29

Applicant: Kwang Ko

Inventor： Kwang Ko

IPC: H01L29/76

CPC classification number: H01L29/0847 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are provided. A current flow path of the high-voltage transistor is widened to reduce on-resistance of the device. Thus, electric characteristics of the device are enhanced. The semiconductor device includes a substrate having a high-voltage transistor area and a PIP capacitor area, an extended drain region disposed in the high-voltage transistor area and separated from a source region, an impurity region formed in an upper portion of the extended drain region, and a drain region formed on a surface of the substrate and disposed within the impurity region.

Abstract translation: 提供了具有高压晶体管和多晶硅 - 绝缘体 - 多晶硅（PIP）电容器的半导体器件及其制造方法。 高压晶体管的电流流路被加宽以减小器件的导通电阻。 因此，提高了装置的电气特性。 半导体器件包括具有高电压晶体管区域和PIP电容器区域的衬底，设置在高压晶体管区域中并与源极区分离的延伸漏极区域，形成在延伸漏极的上部的杂质区域 区域和形成在衬底的表面上并设置在杂质区域内的漏极区域。

公开(公告)号：US20060138549A1

公开(公告)日：2006-06-29

申请号：US11314365

申请日：2005-12-22

Applicant: Kwang Ko

Inventor： Kwang Ko

IPC: H01L29/94

CPC classification number: H01L29/7835 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66659

Abstract: A high-voltage transistor having a low on-resistance and fabricating method thereof are provided. The high-voltage transistor includes a substrate; a shallow-trench isolation layer provided to an upper part of the substrate to a prescribed depth to define an active area; an extended drain region enclosing the shallow-trench isolation layer; a source region provided to an upper part of the substrate to be spaced apart from the extended drain region by a channel area; a drain region provided beneath the shallow-trench isolation layer within the extended drain region; a gate insulating layer pattern provided on the channel area; and a gate conductive layer pattern provided on the gate insulating layer pattern.

Abstract translation: 提供具有低导通电阻的高压晶体管及其制造方法。 高压晶体管包括基板; 将浅沟槽隔离层设置在所述衬底的上部至规定深度以限定有效区域; 包围浅沟槽隔离层的扩展漏极区域; 源极区域，设置在所述衬底的上部，以与所述延伸漏极区域间隔开通道区域; 设置在所述延伸漏极区域内的所述浅沟槽隔离层下方的漏极区域; 设置在通道区域上的栅极绝缘层图案; 以及设置在栅极绝缘层图案上的栅极导电层图案。