公开(公告)号：US07194670B2

公开(公告)日：2007-03-20

申请号：US10708184

申请日：2004-02-13

申请人： Jonathan R. Fales ,  Gregory J. Fredeman ,  Kevin W. Gorman ,  Mark D. Jacunski ,  Toshiaki Kirihata ,  Alan D. Norris ,  Paul C. Parries ,  Matthew R. Wordeman

发明人： Jonathan R. Fales ,  Gregory J. Fredeman ,  Kevin W. Gorman ,  Mark D. Jacunski ,  Toshiaki Kirihata ,  Alan D. Norris ,  Paul C. Parries ,  Matthew R. Wordeman

IPC分类号： G01R31/28

CPC分类号： G11C29/16 ,  G11C29/12015 ,  G11C29/14 ,  G11C2029/0401

摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.

摘要翻译： 公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。 命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。

公开(公告)号：US08582351B2

公开(公告)日：2013-11-12

申请号：US12892191

申请日：2010-09-28

申请人： Igor Arsovski ,  George M. Braceras ,  Kevin W. Gorman ,  Robert M. Houle ,  Harold Pilo

发明人： Igor Arsovski ,  George M. Braceras ,  Kevin W. Gorman ,  Robert M. Houle ,  Harold Pilo

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C8/08

摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.

摘要翻译： 在制造的SRAM中设置字线上电压的方法。 在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。 然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。 提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。

公开(公告)号：US08028195B2

公开(公告)日：2011-09-27

申请号：US12114070

申请日：2008-05-02

申请人： Darren Anand ,  John A. Fifield ,  Kevin W. Gorman

发明人： Darren Anand ,  John A. Fifield ,  Kevin W. Gorman

IPC分类号： G06F11/00

CPC分类号： G01R31/31721 ,  G06F17/505 ,  G06F2217/78

摘要： A design structure embodied in a machine readable medium used in a design process includes a system for indicating status of an on-chip power supply system with multiple power supplies, having a power system status register for receiving digital compliance signals, each compliance signal associated with one of the multiple power supplies, and having an associated compliance level, wherein each digital compliance signal indicates whether its associated power supply is operating at the associated compliance level, and wherein the power system status register generates a power supply status signal based on the digital compliance signals indicating status of the digital compliance signals; and an output for outputting the power supply status signal, wherein if a power supply is operating at its associated compliance level, the power supply status signal indicates that the power supply is passing, otherwise the power supply status signal indicates that the power supply is failing.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括用于指示具有多个电源的片上电源系统的状态的系统，具有用于接收数字符合性信号的电力系统状态寄存器，与 多个电源中的一个并且具有相关联的合规级别，其中每个数字符合信号指示其相关联的电源是否在相关联的合规级别操作，并且其中电力系统状态寄存器基于数字信号产生电源状态信号 指示数字符合信号状态的符合性信号; 以及用于输出电源状态信号的输出，其中如果电源正在其相关联的顺应性水平下操作，则电源状态信号指示电源正在通过，否则电源状态信号指示电源发生故障 。

公开(公告)号：US07631236B2

公开(公告)日：2009-12-08

申请号：US12057405

申请日：2008-03-28

申请人： Kevin W. Gorman ,  Adrian J. Paparelli ,  Michael A. Roberge

发明人： Kevin W. Gorman ,  Adrian J. Paparelli ,  Michael A. Roberge

IPC分类号： G01R31/28 ,  G06F11/00 ,  G11C29/00

CPC分类号： G01R31/31724 ,  G11C29/14 ,  G11C29/16 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72 ,  G11C2029/0401

摘要： Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates command multipliers that are associated with the embedded memory arrays and that selectively operate in one of two different modes: a normal mode or a bypass mode. In the normal mode, instructions from the controller are multiplied so that memory array-specific test functions can be performed locally at the higher operating frequency of each specific memory array. Whereas, in the bypass mode, multiplication of the instructions is suspended so that memory array-specific test functions can be performed locally at the lower operating frequency of the controller. The ability to vary the frequency at which test functions are performed locally, allows for more test pattern flexibility.

摘要翻译： 公开了内置自检（BIST）架构的实施例，其包括以较低频率操作以远程执行多个嵌入式存储器阵列共同的测试功能的独立控制器。 该架构还包含与嵌入式存储器阵列相关联的命令乘法器，并且选择性地以两种不同模式之一操作：正常模式或旁路模式。 在正常模式下，来自控制器的指令相乘，使得存储器阵列特定的测试功能可以在每个特定存储器阵列的较高工作频率下本地执行。 而在旁路模式中，指令的乘法被暂停，使得可以在控制器的较低工作频率下本地执行存储器阵列特定的测试功能。 在本地执行测试功能的频率变化的能力允许更多的测试模式灵活性。

公开(公告)号：US20080215937A1

公开(公告)日：2008-09-04

申请号：US12062599

申请日：2008-04-04

申请人： Jeffrey H. Dreibelbis ,  Kevin W. Gorman ,  Michael R. Nelms

发明人： Jeffrey H. Dreibelbis ,  Kevin W. Gorman ,  Michael R. Nelms

IPC分类号： G11C29/12 ,  G06F11/27

CPC分类号： G11C29/14 ,  G01R31/31724 ,  G01R31/3187 ,  G11C29/16 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72 ,  G11C2029/0401

摘要： Disclosed in a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.

摘要翻译： 公开了一种用于嵌入式存储器阵列的混合内置自检（BIST）架构，将BIST功能分段为远程低速可执行指令和本地高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并使用BIST指令集与多个嵌入式存储器阵列进行通信。 一个高速测试逻辑块被并入被测试的每个嵌入式存储器阵列中，并以更高的频率在本地处理从独立BIST逻辑控制器接收的BIST指令。 高速测试逻辑包括用于将BIST指令的频率从较低频率增加到较高频率的乘法器。 独立的BIST逻辑控制器使多个嵌入式存储器阵列中的多个更高速的测试逻辑结构能够实现。