公开(公告)号：US20110241742A1

公开(公告)日：2011-10-06

申请号：US13028253

申请日：2011-02-16

申请人： Ki Han KIM ,  Hyun Woo LEE

发明人： Ki Han KIM ,  Hyun Woo LEE

IPC分类号： H03L7/06

CPC分类号： G11C7/1072 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  H03L7/0818

摘要： A data output control circuit includes a DLL circuit and a delay detection unit. The DLL circuit is configured to generate a second internal clock by delaying a first internal clock generated from an external clock, compare a phase of the first internal clock with a phase of the second internal clock, and generate a DLL clock. The delay detection unit is configured to generate a sense signal whose logic level is changed according to a comparison result of a set time interval and a delay time interval during which the first internal clock is delayed in order to generate the second internal clock.

摘要翻译： 数据输出控制电路包括DLL电路和延迟检测单元。 DLL电路被配置为通过延迟从外部时钟产生的第一内部时钟来产生第二内部时钟，将第一内部时钟的相位与第二内部时钟的相位进行比较，并生成DLL时钟。 所述延迟检测单元被配置为根据设定的时间间隔的比较结果和延迟所述第一内部时钟的延迟时间间隔来生成其逻辑电平变化的感测信号，以便产生所述第二内部时钟。

公开(公告)号：US20110194529A1

公开(公告)日：2011-08-11

申请号：US12829755

申请日：2010-07-02

申请人： Hee Jeong CHO ,  Ki Seon RYU ,  Jin Sam KWAK ,  Hyun Woo LEE ,  Yong Ho KIM ,  Young Soo YUK

发明人： Hee Jeong CHO ,  Ki Seon RYU ,  Jin Sam KWAK ,  Hyun Woo LEE ,  Yong Ho KIM ,  Young Soo YUK

IPC分类号： H04W36/00 ,  H04W4/00

CPC分类号： H04W48/16 ,  H04L5/0007 ,  H04L5/0037 ,  H04L5/0044

摘要： Ranging by a mobile station in a legacy support mode is disclosed. According to embodiments of the present invention, S-SFH information transmitted by a base station in a system operating in FDM based uplink mixed mode is configured in a manner different from that of the FDM based uplink mixed mode. And, a mobile station performs a ranging by interpreting S-SFH differently according to a presence or non-presence of the mixed mode. Therefore, the present invention efficiently manages the ranging of the mobile station and reduces unnecessary signaling overhead.

摘要翻译： 公开了由传统支持模式的移动台进行测距。 根据本发明的实施例，基于在基于FDM的上行链路混合模式操作的系统中的基站发送的S-SFH信息被配置为与基于FDM的上行链路混合模式不同的方式。 而且，根据混合模式的存在或不存在，移动台通过不同地解释S-SFH来执行测距。 因此，本发明有效地管理移动台的测距，并减少不必要的信令开销。

公开(公告)号：US20110128059A1

公开(公告)日：2011-06-02

申请号：US12648422

申请日：2009-12-29

申请人： Ki Han KIM ,  Hyun Woo LEE

发明人： Ki Han KIM ,  Hyun Woo LEE

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty correction circuit is presented for use in compensating for a duty rate error brought about when a malfunction of a clock signal generator or a failure of a signal transmission line occurs. The duty correction circuit is configured to select one of differential signals as an input signal according to a duty rate. The duty correction circuit is also configured to combine the input signal and a signal obtained by delaying the input signal by a delay time adjusted in accordance to the duty rate. The duty correction circuit is also configured to generate the combined signal as a duty correction signal.

摘要翻译： 提供了一种占空比校正电路，用于补偿当时钟信号发生器发生故障或发生信号传输线路故障时引起的占空比误差。 占空比校正电路被配置为根据占空比来选择差分信号之一作为输入信号。 占空比校正电路还被配置为将输入信号和通过将输入信号延迟通过根据占空比调整的延迟时间而获得的信号组合。 占空比校正电路还被配置为产生组合信号作为占空比校正信号。

公开(公告)号：US20100289542A1

公开(公告)日：2010-11-18

申请号：US12493804

申请日：2009-06-29

申请人： Won Joo YUN ,  Hyun Woo LEE ,  Ki Han KIM

发明人： Won Joo YUN ,  Hyun Woo LEE ,  Ki Han KIM

IPC分类号： H03L7/06 ,  H03K5/04

CPC分类号： H03L7/0814 ,  H03K5/04 ,  H03K5/1565

摘要： A semiconductor integrated circuit includes a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal; a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal; a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.

摘要翻译： 半导体集成电路包括：频率确定单元，被配置为确定半导体集成电路的操作速度并产生频率区域信号; 占空比控制单元，被配置为检测DLL时钟的占空比并产生占空比控制信号; 占空比校正单元，被配置为通过响应于频域信号校正输入时钟的占空比并响应于占空比控制信号来产生校正时钟; 以及被配置为通过控制校正时钟的相位来产生DLL时钟的DLL（延迟锁定环路）。

公开(公告)号：US20100264966A1

公开(公告)日：2010-10-21

申请号：US12493756

申请日：2009-06-29

申请人： Hyun Woo LEE ,  Won Joo YUN

发明人： Hyun Woo LEE ,  Won Joo YUN

IPC分类号： H03L7/06 ,  H03L7/00

CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40611 ,  G11C2211/4067

摘要： A semiconductor integrated circuit includes an update control unit configured to generate an update control signal in response to a first command and a second command; and a DLL (Delay Locked Loop) circuit configured to generate an output clock by controlling a phase of an external clock in response to the update control signal.

摘要翻译： 半导体集成电路包括：更新控制单元，被配置为响应于第一命令和第二命令生成更新控制信号; 以及DLL（延迟锁定环路）电路，被配置为通过响应于更新控制信号控制外部时钟的相位而产生输出时钟。

公开(公告)号：US20090225824A1

公开(公告)日：2009-09-10

申请号：US12348130

申请日：2009-01-02

申请人： Min Seok NOH ,  Yeong Hyeon KWON ,  Jin Sam KWAK ,  Dong Cheol KIM ,  Sung Ho MOON ,  Seung Hee HAN ,  Hyun Woo LEE

发明人： Min Seok NOH ,  Yeong Hyeon KWON ,  Jin Sam KWAK ,  Dong Cheol KIM ,  Sung Ho MOON ,  Seung Hee HAN ,  Hyun Woo LEE

IPC分类号： H04B1/66 ,  H04L27/28

CPC分类号： H04L27/2613 ,  H04L5/0007 ,  H04L5/0048 ,  H04L5/0064

摘要： A method for transmitting a preamble in a scalable bandwidth system is disclosed. The method includes transmitting a primary synchronization channel to which symbols are allocated at intervals of two or more subcarriers, through a specific bandwidth out of an entire system bandwidth at a start time point of a synchronization period, and transmitting a secondary synchronization channel through the specific bandwidth with a prescribed time difference from the primary synchronization channel at the synchronization period. A mobile station can use the same search routine irrespective of a system bandwidth, does not experience any difficulty at a cell edge in establishing signal timing synchronization, can simply perform preamble search, and can transmit a signal in a maximum usable bandwidth, thereby improving the accuracy of location measurement.

摘要翻译： 公开了一种用于在可扩展带宽系统中发送前同步码的方法。 该方法包括：在同步周期的起始时间点，通过特定带宽，在两个或多个子载波的间隔，以整个系统带宽发射符号的主同步信道，以及通过特定的 在同步期间具有与主同步信道的规定时间差的带宽。 无论系统带宽如何，移动站都可以使用相同的搜索程序，在建立信号定时同步时在小区边缘不会遇到任何困难，可以简单地执行前导码搜索，并且可以以最大可用带宽发送信号，从而改善 位置测量精度。

公开(公告)号：US20070262798A1

公开(公告)日：2007-11-15

申请号：US11683500

申请日：2007-03-08

申请人： Won Joo YUN ,  Hyun Woo LEE

发明人： Won Joo YUN ,  Hyun Woo LEE

IPC分类号： H03L7/06

CPC分类号： H03L7/087 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/10

摘要： A delay-locked loop device compensates a skew between an external clock and data or between an external clock and an internal clock particularly by applying a single delay model portion, a complementary phase multiplexing, and a cascade delay line. This device performs an operation by selecting any one of an external clock signal (CLK) and an inverted external clock signal (CLKB) using a multiplexing portion 200, aligning the selected clock signal at a rising edge of the external clock signal (CLK) through a first single coarse delay line 212, a first dual coarse delay line 222, and a first fine delay unit 223 according to the phase comparison with a feedback clock signal (FBCLK) through a delay model portion 250, then receiving a clock signal through the first single coarse delay line 212 to the second single coarse delay line 214 to align the rising edges of the rising clock signal (RCLK) and the falling clock signal (FCLK).

摘要翻译： 延迟锁定环路装置补偿外部时钟和数据之间或外部时钟与内部时钟之间的偏差，特别是通过应用单个延迟模型部分，互补相位复用和级联延迟线。 该装置通过使用多路复用部分200选择外部时钟信号（CLK）和反相外部时钟信号（CLKB）中的任何一个来执行操作，在外部时钟信号（CLK）的上升沿通过选择的时钟信号 根据与延迟模型部分250的反馈时钟信号（FBCLK）的相位比较，第一单个粗略延迟线212，第一双粗略延迟线222和第一精细延迟单元223，然后通过延迟模型部分250接收时钟信号 第一单个粗略延迟线212到第二单个粗略延迟线214，以对准上升时钟信号（RCLK）和下降时钟信号（FCLK）的上升沿。