公开(公告)号：US08103022B2

公开(公告)日：2012-01-24

申请号：US11565576

申请日：2006-11-30

申请人： Hongwei Kong ,  Nelson Sollenberger ,  Li Fung Chang ,  Andy Tong ,  Todd L. Brooks ,  Claude Hayek

发明人： Hongwei Kong ,  Nelson Sollenberger ,  Li Fung Chang ,  Andy Tong ,  Todd L. Brooks ,  Claude Hayek

IPC分类号： H04R3/00 ,  H04B1/38

CPC分类号： H04R5/04 ,  H04R2420/01 ,  H04R2420/07 ,  H04R2499/11

摘要： Methods and systems for detecting, and controlling power for, an auxiliary microphone are disclosed. Aspects of one method may include a detection block intermittently enabling a bias circuit block to provide a bias signal to determine if an auxiliary microphone may be communicatively coupled to a mobile device. The detection block may process 1-bit digital samples received from the bias circuit bock to determine whether the auxiliary microphone may be communicatively coupled. The detection block may also process the 1-bit digital samples to determine if a button associated with the auxiliary microphone may have been pushed or activated.

摘要翻译： 公开了用于检测和控制辅助麦克风的功率的方法和系统。 一种方法的方面可以包括间歇地使得偏置电路块提供偏置信号以确定辅助麦克风是否可通信地耦合到移动设备的检测块。 检测块可以处理从偏置电路块接收的1位数字样本，以确定辅助麦克风是否可以通信耦合。 检测块还可以处理1位数字样本，以确定与辅助麦克风相关联的按钮是否可能被推动或激活。

公开(公告)号：US08018363B2

公开(公告)日：2011-09-13

申请号：US12557352

申请日：2009-09-10

申请人： Todd L. Brooks ,  Kevin L. Miller ,  Josephus A. Van Engelen

发明人： Todd L. Brooks ,  Kevin L. Miller ,  Josephus A. Van Engelen

IPC分类号： H03M3/00

CPC分类号： H03M7/3013

摘要： In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

摘要翻译： 在高保真数字调制器中，提供映射器以最小化多个数模转换器或模数转换器之间的量化噪声，抖动和串扰。 映射器从量化器接收量化电平，并将量化电平映射到输出序列。 映射器包括定义对应于每个量化级别的多个序列的表。 每个序列包括具有多个值之一的两个或多个符号。 映射器还包括选择多个序列之一作为输出序列的发生器。 第一个输出序列的最后一个符号等于下一个输出序列的第一个符号，依此类推。 发生器通过在接收到的每个量化级别的第一和第二序列之间交替来选择输出序列。 发生器通过在接收到的每个奇数值量化电平具有正和负共模能量的序列之间交替来选择输出序列。

公开(公告)号：US20100057471A1

公开(公告)日：2010-03-04

申请号：US12248426

申请日：2008-10-09

申请人： Hongwei Kong ,  Nelson Sollenberger ,  Taiyi Cheng ,  Mark Hahm ,  Todd L. Brooks ,  Xicheng Jiang

发明人： Hongwei Kong ,  Nelson Sollenberger ,  Taiyi Cheng ,  Mark Hahm ,  Todd L. Brooks ,  Xicheng Jiang

IPC分类号： G10L19/00

CPC分类号： H04M1/6025 ,  H04R1/1091 ,  H04R25/554 ,  H04R27/00 ,  H04R2227/003 ,  H04R2420/07

摘要： Aspects of a method and system for processing audio signals via separate input and output processing paths are provided. In this regard, a hardware audio CODEC comprising one or more audio inputs and one or more audio outputs and may be enabled to route, via one or more switching elements, audio signals from any of the inputs to any of the outputs. The CODEC may be enabled to simultaneously process a plurality of audio signals based on a configuration of the switching elements. Upstream from the switching elements, received audio signals may be processed independent of an output to which the may be communicated. Downstream from said switching elements audio signals may be processed independent of an input via which the signals were received.

摘要翻译： 提供了通过单独的输入和输出处理路径处理音频信号的方法和系统的方面。 在这方面，包括一个或多个音频输入和一个或多个音频输出的硬件音频编解码器，并且可以使得能够经由一个或多个开关元件将来自任何输入的音频信号路由到任何输出。 可以使CODEC可以基于开关元件的配置来同时处理多个音频信号。 从开关元件的上游，接收的音频信号可以独立于可以被传送到的输出进行处理。 来自所述开关元件的下游音频信号可以独立于接收信号的输入进行处理。

公开(公告)号：US07211843B2

公开(公告)日：2007-05-01

申请号：US10355260

申请日：2003-01-31

申请人： Khim L. Low ,  Todd L. Brooks ,  Agnes Woo ,  Akira Ito

发明人： Khim L. Low ,  Todd L. Brooks ,  Agnes Woo ,  Akira Ito

IPC分类号： H01L27/10

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to systems and methods for programming a memory cell. More specifically, the present invention relates to a controlled application of current to a memory cell over a controlled time period. The invention utilizes a current mirror configuration having a first transistor and a second transistor, wherein the second transistor is coupled to the memory cell. Programming of the memory cell includes applying a voltage to the first transistor, whereby a first current is generated in the first transistor. A gate of the second transistor is coupled to the first transistor, whereby a second current is generated in the second transistor. The second current is proportional to the first current. The second current is provided to the memory cell, whereby the second current programs the memory cell.

摘要翻译： 本发明涉及用于编程存储器单元的系统和方法。 更具体地说，本发明涉及在受控时间段内对存储器单元的电流的受控应用。 本发明利用具有第一晶体管和第二晶体管的电流镜配置，其中第二晶体管耦合到存储单元。 存储单元的编程包括向第一晶体管施加电压，由此在第一晶体管中产生第一电流。 第二晶体管的栅极耦合到第一晶体管，由此在第二晶体管中产生第二电流。 第二电流与第一电流成比例。 第二电流被提供给存储器单元，由此第二电流对存储单元进行编程。

公开(公告)号：US07049848B2

公开(公告)日：2006-05-23

申请号：US10626701

申请日：2003-07-25

申请人： Todd L. Brooks ,  Anilkumar V. Tammineedi

发明人： Todd L. Brooks ,  Anilkumar V. Tammineedi

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03F1/3205 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/168 ,  H03F2200/331 ,  H03F2200/417 ,  H03F2200/453 ,  H03F2203/45101 ,  H03F2203/5031

摘要： A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. The damping circuit may be a low pass filter. The buffer may be used in an interface circuit that produces an output signal from an input signal and controls the level of the output signal.

公开(公告)号：US06735302B1

公开(公告)日：2004-05-11

申请号：US09579932

申请日：2000-05-26

申请人： Steven L. Caine ,  Todd L. Brooks

发明人： Steven L. Caine ,  Todd L. Brooks

IPC分类号： H04M1900

CPC分类号： H04L25/0278 ,  H03F3/217 ,  H03F3/3008 ,  H03F3/3069 ,  H03F3/68 ,  H04L25/0284 ,  H04L25/0296 ,  H04M19/005

摘要： A CODEC and a SLIC assembly perform current-sensing-voltage synthesis impedance matching and DC feed control functions. Signal processing that does not require high voltage, such as impedance matching and DC feed control, is performed in the digital domain by the CODEC while the SLIC assembly includes high voltage circuitry. This configuration is useful for Voice over Internet Protocol (VOIP) applications with a short subscriber line loop or other long loop applications. The SLIC includes high voltage operational amplifiers (op amps) to drive ring and tip signals. Bipolar transistors are also provided as bias compensating diodes for bias point stabilization over dynamic operating conditions such as temperature. The high voltage op amps include a composite MOSFET-bipolar complimentary symmetry driver stage that offers the bias control and stability of a bipolar device topology and drive capabilities of a power MOSFET device.

摘要翻译： CODEC和SLIC组件执行电流感测电压合成阻抗匹配和直流馈电控制功能。 不需要高电压的信号处理（如阻抗匹配和直流馈电控制）在数字域中由CODEC执行，而SLIC组件包括高压电路。 此配置对于具有短用户线路环路或其他长环路应用的语音互联网协议（VOIP）应用是有用的。 SLIC包括高压运算放大器（运算放大器）来驱动环形和尖端信号。 双极晶体管也被提供作为偏置补偿二极管，用于在诸如温度的动态工作条件下的偏置点稳定。 高压运算放大器包括复合MOSFET - 双极互补对称驱动器级，可提供双极型器件拓扑结构的偏置控制和稳定性以及功率MOSFET器件的驱动能力。

公开(公告)号：US6124813A

公开(公告)日：2000-09-26

申请号：US870981

申请日：1997-06-06

申请人： David Robertson ,  Anthony Del Muro ,  Steve Harston ,  Todd L. Brooks

发明人： David Robertson ,  Anthony Del Muro ,  Steve Harston ,  Todd L. Brooks

IPC分类号： H03M1/06 ,  H03M1/74 ,  H03M3/00

CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/464

摘要： Improved data scramblers and swapper cells and improved digital to analog converters are provided. The improved swapper cells permit data to be propagated through the cell immediately upon receipt. The determination of whether to swap data or pass it directly through is based on a history of data values propagated through the cell, but is independent of the values of the particular inputs being swapped. The data scrambler is structured to permit the possible data inputs on swapper cells in the scrambler to be restricted. A minimum delay data scrambler for use in a fast digital to analog converter is disclosed using these components.

摘要翻译： 提供了改进的数据加扰器和交换器单元以及改进的数模转换器。 改进的交换器单元允许在收到数据后立即传播数据。 是否交换数据或直接传递数据的确定是基于通过单元格传播的数据值的历史记录，而是独立于要交换的特定输入的值。 数据加扰器被构造成允许加扰器中交换器单元上的可能的数据输入被限制。 使用这些组件公开了用于快速数模转换器的最小延迟数据扰频器。

公开(公告)号：US5821807A

公开(公告)日：1998-10-13

申请号：US654306

申请日：1996-05-28

申请人： Todd L. Brooks

发明人： Todd L. Brooks

IPC分类号： G05F1/46 ,  G05F3/30 ,  G05F1/10

CPC分类号： G05F1/461 ,  G05F3/30

摘要： A differential voltage reference circuit implemented in CMOS provides a continuous differential voltage having good substrate and supply noise-rejection and low power consumption. The differential voltage reference is operable under a low voltage power supply in the range of 1-3 volts and does not require a large silicon die area. The differential voltage reference includes two parasitic bipolar transistors and a single differential summing amplifier. PTAT and CTAT differential signals are summed at the amplifier summing junctions to provide a temperature-independent differential reference voltage. The differential amplifier maintains a common-mode level of the output at a constant level with respect to a bias voltage at the bases of the two bipolar transistors.

摘要翻译： CMOS中实现的差分电压参考电路提供了具有良好的衬底和电源噪声抑制和低功耗的连续差分电压。 差分电压基准可在1-3伏范围内的低压电源下工作，不需要大的硅芯片面积。 差分电压基准包括两个寄生双极晶体管和一个单个差分求和放大器。 PTAT和CTAT差分信号在放大器求和点处相加，以提供与温度无关的差分参考电压。 差分放大器将输出的共模电平相对于两个双极晶体管的基极处的偏置电压保持在恒定电平。

公开(公告)号：US5446455A

公开(公告)日：1995-08-29

申请号：US160645

申请日：1993-12-02

申请人： Todd L. Brooks

发明人： Todd L. Brooks

IPC分类号： H03M1/10 ,  H03M1/68 ,  H03M1/74

CPC分类号： H03M1/1009 ,  H03M1/682 ,  H03M1/747

摘要： A current-mode DAC (20) includes two sub-DACs (22, 36), and a calibrated attenuator (48). One sub-DAC (22) receives least-significant-bits (LSB) of a K-bit digital input signal, and the second sub-DAC (36) receives most-significant-bits (MSB) of the K-bit digital input signal. An output of the sub-DAC (22) is attenuated by an attenuator (50), and the attenuated signal is summed with an output of the second sub-DAC (36) to form an analog output signal. A 4-phase gain adjust sample and hold circuit (49) is used to calibrate the attenuator (50). The 4-phase gain adjust sample and hold circuit (49) samples the current from the attenuator (50), and removes device mismatch effects in the attenuator (50) which cause linearity errors in the current-mode DAC (20).

摘要翻译： 电流模式DAC（20）包括两个子DAC（22,36）和校准衰减器（48）。 一个子DAC（22）接收K位数字输入信号的最低有效位（LSB），而第二子DAC（36）接收K位数字输入的最高有效位（MSB） 信号。 子DAC（22）的输出由衰减器（50）衰减，并且衰减的信号与第二子DAC（36）的输出相加以形成模拟输出信号。 四相增益调整采样和保持电路（49）用于校准衰减器（50）。 4相增益调整采样和保持电路（49）对来自衰减器（50）的电流进行采样，并消除衰减器（50）中的电流模式DAC（20）产生线性误差的器件失配效应。

公开(公告)号：US5381112A

公开(公告)日：1995-01-10

申请号：US124684

申请日：1993-09-22

申请人： Mathew A. Rybicki ,  Todd L. Brooks

发明人： Mathew A. Rybicki ,  Todd L. Brooks

IPC分类号： H03F3/45

CPC分类号： H03F3/45121 ,  H03F3/45112 ,  H03F3/45654 ,  H03F3/45717 ,  H03F2203/45408 ,  H03F2203/45418 ,  H03F2203/45424

摘要： A fully differential line driver circuit (25) includes an input differential amplifier (26) and double-ended differential amplifiers (27, 28). A first output driver stage (29) includes a pair of series connected transistors (30, 31), and a second output driver stage includes a pair of series connected transistors (33, 34). The differential amplifiers (27, 28) provide bias and signals voltages to the gates of the series connected transistors (30, 31, 33, 34). The output stages (29, 32) provide differential output signals for driving a low impedance load. The clamping circuits (35-38) control overlap currents in the output stages (29, 32). Common-mode feedback is used to ensure a common-mode voltage of the differential output signals remains at a predetermined voltage to ensure maximum signal swing and thus, maximum efficiency.

摘要翻译： 全差分线路驱动电路（25）包括输入差分放大器（26）和双端差分放大器（27,28）。 第一输出驱动级（29）包括一对串联的晶体管（30,31），第二输出驱动级包括一对串联连接的晶体管（33,34）。 差分放大器（27,28）向串联连接的晶体管（30,31,33,34）的栅极提供偏置和信号电压。 输出级（29,32）提供用于驱动低阻抗负载的差分输出信号。 钳位电路（35-38）控制输出级（29,32）中的重叠电流。 共模反馈用于确保差分输出信号的共模电压保持在预定电压，以确保最大信号摆幅，从而达到最大的效率。