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41.发明授权公开(公告)号：US07049880B2
公开(公告)日：2006-05-23
申请号：US11119675
申请日：2005-05-02
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
摘要翻译： 一种具有双向切换装置的调节电荷泵电路，其在提供精确和稳定的电压输出的第一反馈通路与从电源提供具有低电流消耗的调节电压输出的第二反馈通路之间切换。 第一反馈通道通过调节将电流吸引到电压输出的通过装置来保持精确的电压输出。 第二反馈通道通过控制时钟输入到电荷泵的连接来调节电压输出。 可变电阻用于设置电压输出的稳定电平。 通过使用组合逻辑电路将数字输入信号转换成可变电阻器的控制信号，形成数模转换器。
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公开(公告)号：US06734701B2
公开(公告)日：2004-05-11
申请号：US10323614
申请日：2002-12-18
申请人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
发明人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
IPC分类号： H03K1716
CPC分类号： H03K17/166 , H03K17/165 , H03K19/00361
摘要： An output buffer switch-on control circuit includes several transistors and a discharge current control circuit. A first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source. A second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor. The second transistor also has a second terminal connected to a first terminal of an output capacitor. A third transistor is controlled by the output data source and has a first terminal connected to a common voltage. A fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor. The fourth transistor also has a second terminal connected to the common voltage. The discharge current control circuit is preferably actively-controlled and is connected between a second terminal of the first transistor and a second terminal of the third transistor. The discharge current control circuit preferably includes a discharge resistor and a mirrored current transistor feedback controlled by an output capacitor.
摘要翻译： 输出缓冲器接通控制电路包括多个晶体管和放电电流控制电路。 第一晶体管具有连接到内部电压线并由输出数据源控制的第一端子。 第二晶体管具有连接到内部电压线的第一端子，并由第一晶体管的第二端子控制。 第二晶体管还具有连接到输出电容器的第一端子的第二端子。 第三晶体管由输出数据源控制，并具有连接到公共电压的第一端子。 数字控制第四晶体管，并且具有连接到第二晶体管的第二端子的第一端子。 第四晶体管还具有连接到公共电压的第二端子。 放电电流控制电路优选地被主动地控制并且连接在第一晶体管的第二端子和第三晶体管的第二端子之间。 放电电流控制电路优选地包括放电电阻器和由输出电容器控制的镜像电流晶体管反馈。
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公开(公告)号：US06567318B2
公开(公告)日：2003-05-20
申请号：US09991493
申请日：2001-11-21
申请人： Lorenzo Bedarida , Luca Vandi , Carlo Lisi , Andrea Bellini
发明人： Lorenzo Bedarida , Luca Vandi , Carlo Lisi , Andrea Bellini
IPC分类号： G11C1604
CPC分类号： G05F3/245
摘要： An impedance control circuit controls the impedance of an integrated output driving stage. The integrated output driving stage includes at least one enabling/disabling transistor and at least one driving transistor. The impedance control circuit includes a variable impedance circuit having an impedance that varies with the temperature in correlation with the impedance of the output driving stage. A control circuit is connected to the variable impedance circuit for generating at least one enabling/disabling signal for the at least one enabling/disabling transistor based upon a control signal correlated to the impedance of the variable impedance circuit. The impedance control circuit also includes a current generating circuit for applying to the variable impedance circuit a current which remains substantially stable as the temperature varies.
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公开(公告)号：US07130209B2
公开(公告)日：2006-10-31
申请号：US11128648
申请日：2005-05-12
IPC分类号： G11C17/00
CPC分类号： G11C16/22 , G11C2216/26
摘要： A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.
摘要翻译： 公开了一种用于保护具有多个块的存储器不被修改的方法和系统。 该方法和系统包括提供与OTP单元耦合的多个一次可编程（OTP）单元和OTP单元逻辑。 多个OTP单元的OTP单元对应于多个块的块的一部分。 当OTP小区处于第一状态时，OTP小区允许修改块的部分，并且当OTP小区处于第二状态时永久地防止修改块的部分。 OTP单元逻辑使用多个OTP单元来选择与OTP单元相对应的块的该部分。 当OTP单元处于第二状态时，块的这一部分是写保护的。
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公开(公告)号：US20050189983A1
公开(公告)日：2005-09-01
申请号：US11119675
申请日：2005-05-02
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
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公开(公告)号：US06794927B2
公开(公告)日：2004-09-21
申请号：US10328911
申请日：2002-12-24
申请人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
发明人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/077
摘要： An voltage regulation apparatus for generating a supply voltage internally within an integrated circuit with a modular arrangement of charge pumps. The charge pumps feature a first plurality of parallel-connected blocks of charge pump stages including a first block of charge pump stages, a last block of charge pump stages, and at least one intermediate block of charge pump stages therebetween. Each of the parallel-connected blocks of charge pump stages includes a group of a second plurality of charge pump stages cascade-connected in series; and an output stage connected to an output node. Desired output voltages are obtained by using combinatorial clock signals, generated by a logic circuit, directed to the various charge pump stages.
摘要翻译： 一种电压调节装置，用于在具有电荷泵的模块化布置的集成电路内部产生电源电压。 电荷泵具有第一多个并联连接的电荷泵级的块，包括电荷泵级的第一级，电荷泵级的最后一级，以及其间的至少一个中间电荷泵级。 电荷泵级的每个并联连接的块包括串联级联的第二组多个电荷泵级的组; 以及连接到输出节点的输出级。 通过使用由逻辑电路产生的组合时钟信号来获得期望的输出电压，指向各种电荷泵级。
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公开(公告)号：US5793676A
公开(公告)日：1998-08-11
申请号：US649857
申请日：1996-05-03
摘要： A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address is supplied to the correlating unit which provides for addressing the elementary sectors associated with the addressed composite sector on the basis of the memorized correlation table.
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公开(公告)号：US20130322185A1
公开(公告)日：2013-12-05
申请号：US13485675
申请日：2012-05-31
IPC分类号： G11C5/14
CPC分类号： G11C8/10
摘要： A decoder circuit includes high voltage and low voltage transistors. The decoder circuit uses the high voltage transistors during modify operations to provide a high voltage, e.g., a boosted voltage, to memory cells to change memory cell status or perform other operations. The decoder circuit uses the low voltage transistors during read operations.
摘要翻译： 解码器电路包括高压和低压晶体管。 解码器电路在修改操作期间使用高电压晶体管来向存储器单元提供高电压，例如升压电压，以改变存储器单元状态或执行其他操作。 解码器电路在读取操作期间使用低电压晶体管。
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49.发明申请公开(公告)号：US20050073355A1
公开(公告)日：2005-04-07
申请号：US10753273
申请日：2004-01-07
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
摘要翻译： 一种具有双向切换装置的调节电荷泵电路，其在提供精确和稳定的电压输出的第一反馈通路与从电源提供具有低电流消耗的调节电压输出的第二反馈通路之间切换。 第一反馈通道通过调节将电流吸引到电压输出的通过装置来保持精确的电压输出。 第二反馈通道通过控制时钟输入到电荷泵的连接来调节电压输出。 可变电阻用于设置电压输出的稳定电平。 通过使用组合逻辑电路将数字输入信号转换成可变电阻器的控制信号，形成数模转换器。
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50.发明授权公开(公告)号：US06873551B2
公开(公告)日：2005-03-29
申请号：US10622804
申请日：2003-07-18
申请人： Lorenzo Bedarida , Andrea Sacco , Monica Marziani
发明人： Lorenzo Bedarida , Andrea Sacco , Monica Marziani
CPC分类号： G11C7/14 , G11C7/062 , G11C2207/063
摘要： A configurable mirror sense amplifier system for flash memory having the following features. A power source generates a reference voltage. A plurality of transistors is biased at the reference voltage. The plurality of transistors is each coupled to a second transistor. Each of the plurality of transistors is also configured to provide a current for comparison with the flash memory. The reference voltage is internal, stable and independent from variations of a power supply or temperature. The plurality of transistors is in parallel with one another. A mirror transistor is coupled to the plurality of transistors. The plurality of transistors is configured so that at least one of at least one transistor is activated with a signal in order to provide the current for comparison to the flash memory. Also, the reference voltage may be modified in order to modify the current for comparison to the flash memory.
摘要翻译： 一种用于闪存的可配置的镜像放大器系统，具有以下特征。 电源产生参考电压。 多个晶体管被偏置在参考电压。 多个晶体管各自耦合到第二晶体管。 多个晶体管中的每一个也被配置为提供用于与闪速存储器进行比较的电流。 参考电压是内部的，稳定的，独立于电源或温度的变化。 多个晶体管彼此并联。 反射镜晶体管耦合到多个晶体管。 多个晶体管被配置为使得至少一个晶体管中的至少一个被激活，以便提供用于与闪存相比较的电流。 此外，可以修改参考电压以便修改用于与闪存存储器进行比较的电流。
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