公开(公告)号：US5805435A

公开(公告)日：1998-09-08

申请号：US824958

申请日：1997-03-27

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： H02M3/07 ,  H02M3/18

CPC分类号： H02M3/07

摘要： A device includes a first line at the supply voltage; a second line at the boost voltage; a booster stage; a supply detecting stage connected to the first line and generating a first level signal when the supply voltage exceeds a first predetermined level; a boost detecting stage connected to the second line and generating a second level signal when the boost voltage exceeds a second predetermined level; a regulating stage enabled by the boost detecting stage; and a pump control stage, which generates a regulating enabling signal for the regulating stage in the absence of the first level signal and in the presence of an enabling signal enabling the boost condition. The regulating stage generates a regulating signal in the presence of the second level signal and the regulating enabling signal, when the boost voltage exceeds a third predetermined level; and the pump control stage generates a pump activating signal for the booster stage in the absence of the first level signal and the regulating signal.

摘要翻译： 设备包括在电源电压下的第一线; 在升压电压下的第二行; 增强阶段; 电源检测级连接到第一线，并且当电源电压超过第一预定电平时产生第一电平信号; 升压检测级，连接到第二线，并且当升压电压超过第二预定电平时产生第二电平信号; 由升压检测级使能的调节级; 以及泵控制级，其在没有第一级信号的情况下产生用于调节级的调节使能信号，并且存在能够进行升压状态的使能信号。 当升压电压超过第三预定电平时，调节级在存在第二电平信号和调节使能信号的情况下产生调节信号; 并且在没有第一电平信号和调节信号的情况下，泵控制级产生用于升压级的泵激活信号。

公开(公告)号：US5764570A

公开(公告)日：1998-06-09

申请号：US691796

申请日：1996-08-02

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C16/28 ,  G11C7/00

CPC分类号： G11C16/28

摘要： A reading circuit for a multibit register has a differential stage that is configured as an output latch by one of two control phases required by the circuit after the discrimination phase of a reading cycle a single NOR gate, the output of which is provided with anti-overshoot means, enables the performance of a reading cycle. An input of the differential stage, is connectable to a common sensing line to which all the cells of the register are coupled in an OR configuration, while the other input is connectable to a reference current generator.

摘要翻译： 用于多位寄存器的读取电路具有差分级，其被配置为在读取周期的识别阶段之后电路所需的两个控制相位之一的单个或非门，其输出被提供有反相器 超调意味着能够执行阅读周期。 差分级的输入可连接到公共感测线，寄存器的所有单元以OR配置耦合到该公共感测线，而另一个输入可连接到参考电流发生器。

公开(公告)号：US5734610A

公开(公告)日：1998-03-31

申请号：US690530

申请日：1996-07-31

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C16/26 ,  G11C16/06

CPC分类号： G11C16/26

摘要： A reading circuit includes, for each bit line of a matrix of memory cells, a controllable switching element which can connect the bit line to a voltage source in response to a control signal applied to a control terminal thereof, a detector stage sensitive to the flow of current through the bit line, and a driving stage including two field-effect transistors connected in the inverter configuration with the input of the inverter connected to the bit line and with the output of the inverter connected to the control terminal of the controllable switching element. In order to charge the capacitance associated with the bit line rapidly but without causing oscillatory phenomena, the driving stage includes circuitry for reducing the gain of the feedback loop formed by the inverter and by the controllable switching element.

摘要翻译： 读取电路包括对于存储器单元矩阵的每个位线，可控开关元件，其可响应于施加到其控制端的控制信号而将位线连接到电压源;对流动敏感的检测器级 的电流，以及驱动级，包括以逆变器配置连接的两个场效应晶体管，连接到位线的反相器的输入端连接到反相器的输出端，连接到可控开关元件的控制端子 。 为了快速地对与位线相关的电容进行充电，但不引起振荡现象，驱动级包括用于降低由逆变器和可控开关元件形成的反馈回路的增益的电路。

公开(公告)号：US5731716A

公开(公告)日：1998-03-24

申请号：US592122

申请日：1996-01-26

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C11/56 ,  G11C15/00 ,  G11C15/04 ,  G11C16/04 ,  G11C29/00 ,  G11C29/04 ,  H03K19/177

CPC分类号： G11C29/781 ,  G11C11/56 ,  G11C15/00 ,  G11C16/0441

摘要： A programmable cell and a multibit register composed of a plurality of such cells, specifically for performing a coincidence check between a certain code permanently recorded in the cell or cells and a logic configuration present on a pair or on a plurality of pairs of control lines are disclosed. Each cell has two branches connected in OR configuration to a common sensing line of the cell or of the multibit register. The logic states to be tested for coincidence are applied in a complemented form through a pair of lines to each cell, that is to the two branches of the cell. Each cell, permanently programmed in one or the other of its branches, intrinsically performs a comparison between its permanently programmed logic configuration and the configuration of the complemented control lines associated therewith. A great simplification is achieved in the overall circuitry of a redundance or reconfiguration system.

摘要翻译： 由多个这样的单元组成的可编程单元和多位寄存器，专门用于执行永久记录在单元或单元中的某个代码与存在于一对或多对控制线上的逻辑配置之间的一致性检查， 披露 每个单元有两个分支以OR配置连接到单元或多位寄存器的公共感测线。 通过一对线对每个单元，即单元格的两个分支，以互补的形式应用待测试的逻辑状态。 在其一个或另一个分支中永久编程的每个单元本质地执行其永久编程逻辑配置与与其相关联的补充控制线的配置之间的比较。 在冗余或重新配置系统的整体电路中实现了很大的简化。

公开(公告)号：US08824205B2

公开(公告)日：2014-09-02

申请号：US11279385

申请日：2006-04-11

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C5/06 ,  G11C7/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/24 ,  G11C8/14 ,  G11C8/12 ,  G11C7/18 ,  G11C7/12

CPC分类号： G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

公开(公告)号：US08630115B2

公开(公告)日：2014-01-14

申请号：US13198978

申请日：2011-08-05

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C16/24 ,  G11C16/08 ,  G11C16/06 ,  G11C16/04 ,  G11C5/06 ,  G11C7/02

CPC分类号： G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

摘要翻译： 非易失性电子存储器件被集成在半导体上，并且是具有NAND架构的闪存EEPROM类型，其包括至少一个分为物理扇区的存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列，或者 位线的存储单元。 给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端 行指向源行的相同选择行。

公开(公告)号：US20110286269A1

公开(公告)日：2011-11-24

申请号：US13198978

申请日：2011-08-05

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C16/08 ,  H01S4/00

CPC分类号： G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

摘要翻译： 非易失性电子存储器件被集成在半导体上，并且是具有NAND架构的闪存EEPROM类型，其包括至少一个分为物理扇区的存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列，或者 位线的存储单元。 给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端 行指向源行的相同选择行。

公开(公告)号：US07649778B2

公开(公告)日：2010-01-19

申请号：US12409740

申请日：2009-03-24

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C16/04

CPC分类号： G11C5/066 ,  G11C7/1018 ,  G11C7/1045 ,  G11C16/0483 ,  G11C16/08 ,  G11C2207/105

摘要： A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

摘要翻译： 一种用于以具有至少一个以行或字线和列或位线组织的存储矩阵的NAND架构来访问，读取，编程和擦除闪存EEPROM类型的半导体集成非易失性存储器件的方法，其中 为了存储器，提供了多个附加的地址引脚。 该方法提供异步类型的访问协议和扩展类型的协议，允许通过在两个连续的时钟脉冲中加载与附加引脚相关联的地址寄存器来直接和并行地寻址存储器扩展部分。 还提供了第三个多次访问模式和引用附加地址引脚的并行附加总线，以允许双寻址模式，顺序和并行。

公开(公告)号：US20090256248A1

公开(公告)日：2009-10-15

申请号：US12401464

申请日：2009-03-10

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： H01L23/52 ,  H01L23/498 ,  H01L23/522 ,  H01L21/50

CPC分类号： H01L23/50 ,  H01L23/525 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.

摘要翻译： 用于集成器件的配置端子包括结构独立并连接到相应的第一和第二端子的第一和第二部分，并且其具有适合于选择性地连接到这样的第一和第二端子的至少一个接触端子。 此外，一种方法构成了包括多个地址焊盘和相应的电源引脚的集成器件。 该方法包括：实现至少一个配置终端，其具有在结构上独立且连接到至少一个接触终端的第一和第二部分; 提供这样的第一和第二部分与相应的端子的接触; 以及通过所述接触端子与至少一个所述端子的短路来配置所述装置。

公开(公告)号：US07295472B2

公开(公告)日：2007-11-13

申请号：US11279384

申请日：2006-04-11

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C11/34

CPC分类号： G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

摘要： A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix divided into sectors being singularly erasable and organized in rows or word lines and columns or bit lines of memory cells. Advantageously, the matrix may include logic sectors wherein pairs of rows or word lines are electrically short-circuited and refer to a single biasing terminal, source terminals of the associated cells of each pair of rows associated with a same source select line referring to a corresponding biasing terminal, and at least one pair of independent drain select lines, each of the rows and of the lines being provided with metallization shunts to by-pass groups of bit lines and/or to speed up the propagation times of the biasing in the corresponding logic sector.

摘要翻译： 非易失性存储器电子器件集成在半导体上，并且是具有NAND型结构的闪存EEPROM类型，包括被划分成扇区的至少一个存储器矩阵，其被单独地擦除并且被组织成行或字线和列或位线 的记忆细胞。 有利地，矩阵可以包括其中行或字线对被电短路并且指代单个偏置端子的逻辑扇区，每对行的相关联的单元的源极端子与相应的源选择线相关联，其指向相应的 偏置端子以及至少一对独立的漏极选择线，行和行中的每一行被设置有金属化分流器以逐行排列组和/或加速相应的偏置的传播时间 逻辑部门。