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公开(公告)号：US20240236059A1
公开(公告)日：2024-07-11
申请号：US18615674
申请日：2024-03-25
Applicant: Mellanox Technologies, Ltd.
Inventor： Barak Gafni , Liron Mula
CPC classification number: H04L63/0485 , H04L63/162 , H04L63/164 , H04L12/4633 , H04L63/0428
Abstract: Technologies for bi-directional encryption and decryption for underlay and overlay operations are described. One network device a path-selection circuit that operates in a first mode or a second mode. In the first mode, the path-selection circuit receives a first incoming packet on a first port, sends it to a security circuitry to decrypt the first incoming packet to obtain a first decrypted packet, sends the first decrypted packet to a processing circuitry to process the first decrypted packet to obtain a first outgoing packet, and sends the first outgoing packet to a second port of the network device. In the second mode, the path-selection circuit receives a second incoming packet on a third port, sends it to the processing circuitry to de-encapsulate the second incoming packet to obtain a second outgoing packet, and sends the second outgoing packet to a fourth port of the network device.
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公开(公告)号：US12028155B2
公开(公告)日：2024-07-02
申请号：US17534776
申请日：2021-11-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Bar Shapira , Ariel Almog , Dotan David Levi , Natan Manevich , Thomas Kernen , Liron Mula
IPC: H04J3/06
CPC classification number: H04J3/0638
Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.
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公开(公告)号：US11956160B2
公开(公告)日：2024-04-09
申请号：US17336080
申请日：2021-06-01
Applicant: Mellanox Technologies, Ltd.
Inventor： Zachy Haramaty , Liron Mula , Alon Singer , Eduard Kvetny , Aviv Kfir
CPC classification number: H04L47/35 , H04L45/22 , H04L47/39 , H04L49/90 , H04L63/0428 , H04L63/164
Abstract: An apparatus includes an input interface to receive incoming packets from a first network device and an output interface to send outgoing packets to a second network device. Media access control security (MACsec) circuitry is coupled between the input interface and the output interface. Bypass flow-control (FC) circuitry is coupled between the input interface and the MACsec circuitry. The bypass FC circuitry is to detect an FC packet in the incoming packets and pass the FC packet passively to the output interface to enable end-to-end flow control directly between the first network device and the second network device.
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公开(公告)号：US11888753B2
公开(公告)日：2024-01-30
申请号：US17398677
申请日：2021-08-10
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Liron Mula , Zachy Haramaty , Shachar Bar Tikva , Dekel Dadon
IPC: H04L12/823 , H04L47/32 , H04L47/30
Abstract: A relay device is provided that may identify a quantity of empty data byte locations in a data buffer of the relay device. The relay device may receive an indicator associated with transmitting data packets. The relay device may pause or enable a lossless flow of data between the relay device, a host device, and a peer device based on the quantity of empty data byte locations, the indicator, or both. The relay device may include a first data interface coupled with a peer device, a second data interface coupled with a host device, a data buffer configured to store data packets received from the host device, and a state machine that enables a lossless transmission of data between the host device and peer device. The state machine may transmit a pause frame to the host device based on a data buffer utilization reaching a data storage capacity.
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公开(公告)号：US20230163869A1
公开(公告)日：2023-05-25
申请号：US17534776
申请日：2021-11-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Bar Shapira , Ariel Almog , Dotan David Levi , Natan Manevich , Thomas Kernen , Liron Mula
IPC: H04J3/06
CPC classification number: H04J3/0638
Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.
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Patent Agency Ranking
公开(公告)号：US20230132571A1
公开(公告)日：2023-05-04
申请号：US17520093
申请日：2021-11-05
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Paraskevas Bakopoulos , Ioannis (Giannis) Patronas , Dimitris Syrivelis , Liron Mula , Aviad Levy , Elad Mentovich
Abstract: Devices, networking devices, and switches, among other things, are disclosed. An illustrative switch is disclosed to include a plurality of optical Input/Output (I/O) ports; a multi-chip module (MCM) assembly including switching circuitry and at least one chiplet that is optically coupled with one of the plurality of optical I/O ports; and a controller coupled with the at least one chiplet and configured to couple the at least one chiplet with a Quantum Key Distribution (QKD) device.
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公开(公告)号：US20230127568A1
公开(公告)日：2023-04-27
申请号：US17508998
申请日：2021-10-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Gil Levy , Liron Mula , Barak Gafni
Abstract: A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with. the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.
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公开(公告)号：US20230120745A1
公开(公告)日：2023-04-20
申请号：US17503383
申请日：2021-10-18
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Niv Aibester , Gil Levy , Liron Mula , Barak Gafni , Aviv Kfir
IPC: H04L12/861 , H04L12/879 , H04L12/933 , H04L12/925 , H04L12/911
Abstract: A network device includes multiple ports, packet processing circuitry, a memory and a reserved-memory management circuit (RMMC). The ports are to communicate packets over a network. The packet processing circuitry is to process the packets using a plurality of queues. The memory is to store a shared buffer. The RMMC is to allocate segments of the shared buffer to the queues, including allocating reserve segments of the shared buffer to selected queues that meet a reserve-allocation criterion.
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公开(公告)号：US20220385590A1
公开(公告)日：2022-12-01
申请号：US17336080
申请日：2021-06-01
Applicant: Mellanox Technologies, Ltd.
Inventor： Zachy Haramaty , Liron Mula , Alon Singer , Eduard Kvetny , Aviv Kfir
IPC: H04L12/801 , H04L12/861 , H04L12/707 , H04L29/06
Abstract: An apparatus includes an input interface to receive incoming packets from a first network device and an output interface to send outgoing packets to a second network device. Media access control security (MACsec) circuitry is coupled between the input interface and the output interface. Bypass flow-control (FC) circuitry is coupled between the input interface and the MACsec circuitry. The bypass FC circuitry is to detect an FC packet in the incoming packets and pass the FC packet passively to the output interface to enable end-to-end flow control directly between the first network device and the second network device.
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公开(公告)号：US11476928B2
公开(公告)日：2022-10-18
申请号：US16921993
申请日：2020-07-07
Applicant: Mellanox Technologies, Ltd.
Inventor： Dotan David Levi , Avi Urman , Lior Narkis , Liron Mula , Paraskevas Bakopoulos , Ariel Almog , Roee Moyal , Gal Yefet
IPC: H04B7/26 , H04L49/351 , H04L49/90 , H04W72/04 , H04W74/08
Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound packets, which are received from the communication network, depending on the timeslots.
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