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    MEMORY SYSTEM FAILURE DETECTION AND SELF RECOVERY OF MEMORY DICE
    42.
    发明公开
    MEMORY SYSTEM FAILURE DETECTION AND SELF RECOVERY OF MEMORY DICE 审中-公开

    公开(公告)号：US20230393955A1

    公开(公告)日：2023-12-07

    申请号：US17877779

    申请日：2022-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Robert Mason ,  Scott A. Stoller ,  Pitamber Shukla ,  Kenneth W. Marr ,  Chi Ming Chu ,  Hossein Afkhami

    IPC: G06F11/14 ,  G06F9/30

    CPC classification number: G06F11/1471 ,  G06F9/30098 ,  G06F11/1469

    Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

    MEMORY SUB-SYSTEM FOR MEMORY CELL TOUCH-UP
    43.
    发明公开
    MEMORY SUB-SYSTEM FOR MEMORY CELL TOUCH-UP 审中-公开

    公开(公告)号：US20230377664A1

    公开(公告)日：2023-11-23

    申请号：US17747761

    申请日：2022-05-18

    Applicant: Micron Technology, Inc.

    Inventor： Bin Wang ,  Pitamber Shukla ,  Scott A. Stoller

    IPC: G11C16/34 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C16/102

    Abstract: An apparatus can include a touch-up component. The touch-up component can detect that at least one memory cell of a page of memory cells has lost a portion of a charge. The touch-up component can set touch-up parameters for the page of memory cells. The touch-up component can cause a transfer of data from the page of memory cells to a cache. The touch-up component can reprogram the at least one memory cell using the set touch-up parameters.

    Power loss immunity in memory programming operations
    46.
    发明授权
    Power loss immunity in memory programming operations 有权

    公开(公告)号：US11594292B2

    公开(公告)日：2023-02-28

    申请号：US17238818

    申请日：2021-04-23

    Applicant: Micron Technology, Inc.

    Inventor： Scott A. Stoller ,  Pitamber Shukla ,  Kishore Kumar Muchherla ,  Fulvio Rori ,  Bin Wang

    IPC: G11C16/06 ,  G11C16/34 ,  G11C16/08 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24

    Abstract: Described are systems and methods for providing power loss immunity in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a programming pulse to be applied to to one or more wordlines of the memory array; responsive to determining that a threshold voltage of one or more memory cells of the memory array has reached a pre-program verify level, causing a first bias voltage level to be applied to a first subset of bitlines of the memory array and causing a second bias voltage level to be applied to a second subset of bitlines of the memory array.

    CHARGE LOSS TRACKING THROUGH TARGETED BIT COUNT
    49.
    发明公开
    CHARGE LOSS TRACKING THROUGH TARGETED BIT COUNT 审中-公开

    公开(公告)号：US20240363188A1

    公开(公告)日：2024-10-31

    申请号：US18647731

    申请日：2024-04-26

    Applicant: Micron Technology, Inc.

    Inventor： Steven Michael Kientz ,  Pitamber Shukla ,  Tarun Singh Yadav

    IPC: G11C29/50

    CPC classification number: G11C29/50004

    Abstract: Memory cells may store multiple bits per cell. For example, three-level cell (TLC) memory stores three bits per cell using eight voltage levels. The number of memory cells at each voltage is approximately the total number of cells divided by the number of voltage levels. The number of memory cells above a certain read voltage is the CFByte value for the read voltage. Based on a difference between the CFByte value and a target CFByte value for the read voltage, an adjustment value is determined. Characteristics of an individual memory device may be determined by finding several CFByte values for a small range of read voltages. Using the gathered CFByte values, a DAC adjustment value is determined for the individual memory device.

    MEMORY PILLAR SELECTION TRANSISTOR EVALUATION
    50.
    发明公开
    MEMORY PILLAR SELECTION TRANSISTOR EVALUATION 审中-公开

    公开(公告)号：US20240355392A1

    公开(公告)日：2024-10-24

    申请号：US18640902

    申请日：2024-04-19

    Applicant: Micron Technology, Inc.

    Inventor： Avinash Rajagiri ,  Pitamber Shukla

    IPC: G11C16/04 ,  G11C16/10 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    CPC classification number: G11C16/0483 ,  G11C16/10 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: Methods, systems, and devices for memory pillar selection transistor evaluation are described. A memory system may be configured to monitor threshold voltage characteristics of pillar selection transistors, which may include evaluations relative to certain subsets of the pillar selection transistors. For example, an activation voltage may be applied to the pillar selection transistors to determine whether threshold voltages associated with each subset of pillar selection transistors have shifted. Determining whether the threshold voltages have shifted may include determining whether an access parameter has been satisfied, such as a duration to program memory cells. For example, a relatively long duration may indicate that channels associated with pillar selection transistors have become less conductive for a given activation voltage.

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