公开(公告)号：US20240038311A1

公开(公告)日：2024-02-01

申请号：US17874828

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Ankit V. Vashi ,  Zhenming Zhou ,  Jung Sheng Hoei

IPC: G11C16/34 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C16/349 ,  G11C16/08

Abstract: A method includes designating a first subset of non-volatile memory with a first reliability designation, designating a second subset of non-volatile memory blocks with a second reliability designation, configuring the first subset of non-volatile memory blocks and the second subset of non-volatile memory blocks in a first verification mode, writing data to first subset of non-volatile memory blocks and the second subset of non-volatile memory blocks in the absence of write verification.

公开(公告)号：US20230393777A1

公开(公告)日：2023-12-07

申请号：US17830802

申请日：2022-06-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yu-Chung Lien ,  Li-Te Chang ,  Zhenming Zhou

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0679

Abstract: A first page read on the first memory page utilizing a first trim value is performed responsive to initiating a memory page scan on a first memory page of a plurality of memory pages. Whether a first data state metric associated with the first page read satisfies a first threshold criterion is determined. A second page read on the first memory page utilizing a second trim value is performed responsive to determining that the first data state metric satisfies the first threshold criterion. Whether a second data state metric associated with the second page read satisfies a second threshold criterion is determined. The second trim value to perform subsequent page reads during memory page scans is selected responsive to determining that the second data state metric does not satisfy the first threshold criterion.

公开(公告)号：US20250104796A1

公开(公告)日：2025-03-27

申请号：US18786016

申请日：2024-07-26

Applicant: Micron Technology, Inc.

Inventor： Jun Wan ,  Yu-Chung Lien ,  Zhenming Zhou

IPC: G11C29/52 ,  G11C16/34

Abstract: Devices, methods, and systems for performing corrective sense operations in memory are described herein. An example apparatus includes a memory component including a plurality of groups of memory cells, and a processing device coupled to the memory component and configured to perform a sense operation on the plurality of groups of memory cells, perform a corrective sense operation on a first one of the plurality of groups of memory cells using a corrective value, and perform the corrective sense operation on a second one of the plurality of groups of memory cells using the corrective value.

公开(公告)号：US20250087283A1

公开(公告)日：2025-03-13

申请号：US18771479

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  John Paul Aglubat ,  Zhenming Zhou

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/12

Abstract: Access line voltage ramp rate adjustment is described herein. An apparatus may include a memory device including a plurality of groups of memory cells and a processing device coupled to the memory device which may receive a program command to be executed on one of the plurality of groups of memory cells and determine if a program verify (PVFY) loop associated with the program command is below a threshold for a subblock of the memory device that includes the one of the plurality of groups. Responsive to a determination that the PVFY loop is not below the threshold, the program command can be executed. Responsive to a determination that the PVFY loop is below the threshold, an unselected access line voltage ramp rate for the subblock can be adjusted to a slower rate, and the program command can be executed using the adjusted unselected access line voltage ramp rate.

公开(公告)号：US20250085863A1

公开(公告)日：2025-03-13

申请号：US18779926

申请日：2024-07-22

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Huai-Yuan Tseng ,  Tomer Tzvi Eliash ,  Zhenming Zhou

IPC: G06F3/06

Abstract: A processing device, operatively coupled with a memory device, receives a request to perform a programming operation on a first set of cells addressable by a first wordline of a first die of the memory device. The processing device identifies a programming order associated with the first wordline. The processing device adjusts, based on the programming order, a biasing scheme associated with the first wordline. The processing device further performs, using the programming order and biasing scheme, the programming operation on the first set of cells addressable by the first wordline.

公开(公告)号：US12237015B2

公开(公告)日：2025-02-25

申请号：US17888225

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Vivek Shivhare ,  Vinh Diep ,  Zhenming Zhou

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C29/52

Abstract: Methods, systems, and apparatuses include determining an operation type for an operation. A sensing time is elected using the operation type. The operation is executed using the sensing time.

公开(公告)号：US12211556B2

公开(公告)日：2025-01-28

申请号：US17887348

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Zhenming Zhou

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26

Abstract: A method includes determining that a program operation includes a first pass to apply a first voltage distribution to a plurality of memory cells and a second pass to apply a second voltage distribution to the plurality of memory cells, performing the first pass of the program operation using a first sensing time, and performing the second pass of the program operation using a second sensing time during the second pass of the program operation, where the first sensing time is shorter than the second sensing time.

公开(公告)号：US12189961B2

公开(公告)日：2025-01-07

申请号：US17889873

申请日：2022-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yu-Chung Lien ,  Zhenming Zhou

IPC: G06F12/00 ,  G06F3/06

Abstract: A program command specifying new data to be programmed is received and partitioned into a plurality of data partitions. A wordline addressing a first set of memory cells to be programmed with a data partition of the plurality of data partitions is identified for a specified block of the memory device. Existing data stored by a second set of memory cells is read. An expected data state metrics is produced for each data partition of the plurality of data partitions. A data partition associated with a lowest expected data state metric among the plurality of expected data state metrics is identified. The identified data partition is programmed to the identified wordline.

公开(公告)号：US12148480B2

公开(公告)日：2024-11-19

申请号：US17891544

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Jun Wan ,  Zhenming Zhou

IPC: G11C16/26 ,  G11C16/04

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. The set of memory components includes a processing device that initiates a corrective read (CR) operation on a set of memory components. The set of memory components includes a pillar that includes a channel and a plurality of transistors. The processing device applies a charge to a first word line (WL) comprising a first transistor of a plurality of transistors to neutralize charges in the channel and senses a charge distribution of a second WL comprising a second transistor of the plurality of transistors adjacent to the first transistor based on the charge applied to the first WL that neutralized the charges in the channel.

公开(公告)号：US12142326B2

公开(公告)日：2024-11-12

申请号：US17752590

申请日：2022-05-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yu-Chung Lien ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04

Abstract: A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device. The processing device is further to determine a value of a metric reflecting a state of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a programming operation with respect to the subset of memory cells. The programming operation includes the delay between a first pass of the programming operation and a second pass of the programming operation.