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公开(公告)号：US20250111886A1
公开(公告)日：2025-04-03
申请号：US18979331
申请日：2024-12-12
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Zhenming Zhou , Ting Luo
Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.
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公开(公告)号：US20240386972A1
公开(公告)日：2024-11-21
申请号：US18787787
申请日：2024-07-29
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Murong Lang , Li-Te Chang
IPC: G11C16/34 , G11C11/406
Abstract: An example system can include a memory device and a processing device. The memory device can include a group of memory cells. The processing device can be coupled to the memory device. The processing device can be configured to determine a distance of a memory die from a center of a memory component. The processing device can be configured to perform a read disturb operation on the memory die based on the determined distance use a first voltage window for a set of memory cells of the group of memory cells during a first time period.
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公开(公告)号：US12073905B2
公开(公告)日：2024-08-27
申请号：US17894528
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Yu-Chung Lien , Murong Lang , Zhenming Zhou , Michael G. Miller
CPC classification number: G11C29/52 , G11C16/08 , G11C16/102 , G11C16/3404
Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.
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公开(公告)号：US20240045595A1
公开(公告)日：2024-02-08
申请号：US17880213
申请日：2022-08-03
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Charles See Yeung Kwong , Vamsi Pavan Rayaprolu , Seungjune Jeon , Zhenming Zhou
CPC classification number: G06F3/0616 , G06F3/0653 , G06F3/0679 , G06N20/00
Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, one or more read margin levels corresponding to a page type associated with the memory device are determined. A machine learning model is applied to the one or more read margin levels to generate a margin prediction value based on the page type and a wordline group associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.
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公开(公告)号：US20230393777A1
公开(公告)日：2023-12-07
申请号：US17830802
申请日：2022-06-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yu-Chung Lien , Li-Te Chang , Zhenming Zhou
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0644 , G06F3/0679
Abstract: A first page read on the first memory page utilizing a first trim value is performed responsive to initiating a memory page scan on a first memory page of a plurality of memory pages. Whether a first data state metric associated with the first page read satisfies a first threshold criterion is determined. A second page read on the first memory page utilizing a second trim value is performed responsive to determining that the first data state metric satisfies the first threshold criterion. Whether a second data state metric associated with the second page read satisfies a second threshold criterion is determined. The second trim value to perform subsequent page reads during memory page scans is selected responsive to determining that the second data state metric does not satisfy the first threshold criterion.
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Patent Agency Ranking
公开(公告)号：US12198777B2
公开(公告)日：2025-01-14
申请号：US17812612
申请日：2022-07-14
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Zhenming Zhou , Ting Luo
Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.
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公开(公告)号：US20240062834A1
公开(公告)日：2024-02-22
申请号：US17891852
申请日：2022-08-19
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Zhenming Zhou
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0679 , G06F3/0629
Abstract: A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event in the memory sub-system, and in response, identifies a memory die of a plurality of memory dies in the memory sub-system. The processing device further determines a read margin associated with a first distribution of memory cells of the identified memory die, and determines an adaptive scan frequency for the identified memory die based on the read margin associated with the first distribution of memory cells.
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公开(公告)号：US20240029802A1
公开(公告)日：2024-01-25
申请号：US17871689
申请日：2022-07-22
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Murong Lang , Li-Te Chang
IPC: G11C16/34 , G11C11/406
CPC classification number: G11C16/3418 , G11C16/349 , G11C11/40618
Abstract: An example system can include a memory device and a processing device. The memory device can include a group of memory cells. The processing device can be coupled to the memory device. The processing device can be configured to determine a distance of a memory die from a center of a memory component. The processing device can be configured to perform a read disturb operation on the memory die based on the determined distance use a first voltage window for a set of memory cells of the group of memory cells during a first time period.
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公开(公告)号：US20250138996A1
公开(公告)日：2025-05-01
申请号：US18383712
申请日：2023-10-25
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Charles S. Kwong , Wei Wang , Murong Lang , Shenming Zhou
IPC: G06F12/02
Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a first read level offset associated with reading a first set of data from a first level using a first read level of a plurality of read levels. The controller applies the first read level offset to a machine learning model to estimate a second read level offset, associated with reading a second set of data from a second level of the plurality of levels, using a second read level of the plurality of read levels. The controller updates, based on the first read level offset and the estimated second read level offset, a look-up table that includes a set of read level offsets used to read data from the plurality of levels of the individual component.
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公开(公告)号：US20240363190A1
公开(公告)日：2024-10-31
申请号：US18771393
申请日：2024-07-12
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Yu-Chung Lien , Murong Lang , Zhenming Zhou , Michael G. Miller
CPC classification number: G11C29/52 , G11C16/08 , G11C16/102 , G11C16/3404
Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation; identifying a block family associated with a set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.
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