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公开(公告)号：US08290107B2
公开(公告)日：2012-10-16
申请号：US12320472
申请日：2009-01-27
申请人： Masayuki Takase , Hideki Endo , Koji Fukuda , Kenichi Sakamoto
发明人： Masayuki Takase , Hideki Endo , Koji Fukuda , Kenichi Sakamoto
CPC分类号： H04L7/033
摘要： A clock data recovery circuit that supplies stable reference clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2π. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reference clock.
摘要翻译： 一种时钟数据恢复电路，其分别通过缩短与接收的突发数据信号中包含的抖动分量的每个接收的脉冲数据信号的位同步时间来分别提供稳定的参考时钟，包括产生具有相同时钟的参考时钟的内插器 频率与接收到的突发数据信号的频率相同，并且具有与参考时钟的相位不同的相位的两种类型的确定时钟; 以及可以以M / 2＆amp; pgr为单位改变参考时钟的相位的相位调整控制电路。 在开始接收到脉冲串数据信号之后，时钟数据恢复电路在第一相位调整定时设置较大的相位变化值，并且减小第二次和随后的相位调整定时中的变化值，从而实现与所接收的脉冲串数据的快速位同步 信号产生参考时钟。
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公开(公告)号：US20100135162A1
公开(公告)日：2010-06-03
申请号：US12699328
申请日：2010-02-03
IPC分类号： H04L12/26
CPC分类号： H04L45/22 , H04L45/021 , H04L45/04 , H04L45/245 , H04L45/28 , H04L45/50 , H04L45/54 , H04L47/41 , Y02D50/30
摘要： A link aggregation function and maintenance function by MPLS OAM. Identical entry information is stored in plural circuits IF which perform a LA setting. In this way, multiplexing to the same LSP is possible even with different IF. The first network IF is assumed to be OAM ACT, and the second network IF is set to OAM SBY (SBY). OAM frame insertion is performed only by an OAM ACT port. In this way, in an opposite MPLS transmission apparatus, it is possible to prevent CV frame reception above a specified number of frames. Further, a switch forwarding table is set to forward frames from the network side to the first network IF of OAM ACT. The second network IF which was set to OAM SBY does not perform fault detection by CV reception. In this way, incorrect detection of faults due to non-reception of OAM can be prevented.
摘要翻译： MPLS OAM的链路聚合功能和维护功能。 相同条目信息存储在执行LA设置的多个电路IF中。 以这种方式，即使使用不同的IF，也可以复用到相同的LSP。 第一个网络IF被假定为OAM ACT，第二个网络IF设置为OAM SBY（SBY）。 OAM帧插入仅由OAM ACT端口执行。 以这种方式，在相反的MPLS传输装置中，可以防止CV帧接收高于指定帧数。 此外，设置交换机转发表将帧从网络侧转发到OAM ACT的第一网络IF。 设置为OAM SBY的第二个网络IF不通过CV接收执行故障检测。 以这种方式，可以防止由于不接收OAM导致的故障的错误检测。
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公开(公告)号：US07675859B2
公开(公告)日：2010-03-09
申请号：US11841277
申请日：2007-08-20
IPC分类号： G08C15/00
CPC分类号： H04L45/22 , H04L45/021 , H04L45/04 , H04L45/245 , H04L45/28 , H04L45/50 , H04L45/54 , H04L47/41 , Y02D50/30
摘要： A link aggregation function and maintenance function by MPLS OAM. Identical entry information is stored in plural circuits IF which perform a LA setting. In this way, multiplexing to the same LSP is possible even with different IF. The first network IF is assumed to be OAM ACT, and the second network IF is set to OAM SBY (SBY). OAM frame insertion is performed only by an OAM ACT port. In this way, in an opposite MPLS transmission apparatus, it is possible to prevent CV frame reception above a specified number of frames. Further, a switch forwarding table is set to forward frames from the network side to the first network IF of OAM ACT. The second network IF which was set to OAM SBY does not perform fault detection by CV reception. In this way, incorrect detection of faults due to non-reception of OAM can be prevented.
摘要翻译： MPLS OAM的链路聚合功能和维护功能。 相同条目信息存储在执行LA设置的多个电路IF中。 以这种方式，即使使用不同的IF，也可以复用到相同的LSP。 第一个网络IF被假定为OAM ACT，第二个网络IF设置为OAM SBY（SBY）。 OAM帧插入仅由OAM ACT端口执行。 以这种方式，在相反的MPLS传输装置中，可以防止CV帧接收高于指定帧数。 此外，设置交换机转发表将帧从网络侧转发到OAM ACT的第一网络IF。 设置为OAM SBY的第二个网络IF不通过CV接收执行故障检测。 以这种方式，可以防止由于不接收OAM导致的故障的错误检测。
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公开(公告)号：US07983267B2
公开(公告)日：2011-07-19
申请号：US12699328
申请日：2010-02-03
IPC分类号： H04L12/56
CPC分类号： H04L45/22 , H04L45/021 , H04L45/04 , H04L45/245 , H04L45/28 , H04L45/50 , H04L45/54 , H04L47/41 , Y02D50/30
摘要： A link aggregation function and maintenance function by MPLS OAM. Identical entry information is stored in plural circuits IF which perform a LA setting. In this way, multiplexing to the same LSP is possible even with different IF. The first network IF is assumed to be OAM ACT, and the second network IF is set to OAM SBY (SBY). OAM frame insertion is performed only by an OAM ACT port. In this way, in an opposite MPLS transmission apparatus, it is possible to prevent CV frame reception above a specified number of frames. Further, a switch forwarding table is set to forward frames from the network side to the first network IF of OAM ACT. The second network IF which was set to OAM SBY does not perform fault detection by CV reception. In this way, incorrect detection of faults due to non-reception of OAM can be prevented.
摘要翻译： MPLS OAM的链路聚合功能和维护功能。 相同条目信息存储在执行LA设置的多个电路IF中。 以这种方式，即使使用不同的IF，也可以复用到相同的LSP。 第一个网络IF被假定为OAM ACT，第二个网络IF设置为OAM SBY（SBY）。 OAM帧插入仅由OAM ACT端口执行。 以这种方式，在相反的MPLS传输装置中，可以防止CV帧接收高于指定帧数。 此外，设置交换机转发表将帧从网络侧转发到OAM ACT的第一网络IF。 设置为OAM SBY的第二个网络IF不通过CV接收执行故障检测。 以这种方式，可以防止由于不接收OAM导致的故障的错误检测。
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公开(公告)号：US20090232265A1
公开(公告)日：2009-09-17
申请号：US12320472
申请日：2009-01-27
申请人： Masayuki Takase , Hideki Endo , Koji Fukuda , Kenichi Sakamoto
发明人： Masayuki Takase , Hideki Endo , Koji Fukuda , Kenichi Sakamoto
IPC分类号： H04L7/00
CPC分类号： H04L7/033
摘要： A clock data recovery circuit that supplies stable reproduction clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2π. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reproduction clock.
摘要翻译： 一种时钟数据恢复电路，其分别通过缩短与所接收的突发数据信号的比特同步的时间，而不管包括在接收的突发数据信号中的抖动分量如何，向对象提供稳定的再现时钟，该内插器产生具有相同的参考时钟 频率与接收到的突发数据信号的频率相同，并且具有与参考时钟的相位不同的相位的两种类型的确定时钟; 以及可以以M / 2pi为单位改变参考时钟的相位的相位调整控制电路。 在开始接收到脉冲串数据信号之后，时钟数据恢复电路在第一相位调整定时设置较大的相位变化值，并且减小第二次和随后的相位调整定时中的变化值，从而实现与所接收的脉冲串数据的快速位同步 信号以产生再现时钟。
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公开(公告)号：US07120160B2
公开(公告)日：2006-10-10
申请号：US10042351
申请日：2002-01-11
IPC分类号： H04L12/56
CPC分类号： H04L49/3045 , H04L49/101 , H04L49/254 , H04L49/50
摘要： A packet switching system arbitrates between Virtual Output Queues (VoQ) in plural input buffers, so as to grant the right of transmitting data to a crossbar switch to some of the VoQs by taking both an output data interval of a VoQ and the queue length of a VoQ as parameters. The system suppresses the delay time of the segment of a VoQ having a high load, thereby preventing buffers from overflowing; and, also, the system permits a VoQ having a low load to transmit segments under no influence of the VoQ that has a high load and is just reading out the segment.
摘要翻译： 分组交换系统在多个输入缓冲器中的虚拟输出队列（VoQ）之间进行仲裁，以便通过同时获取VoQ的输出数据间隔和VoQ的队列长度来授予向某些VoQ发送数据到交叉开关的权利 一个VoQ作为参数。 该系统抑制具有高负载的VoQ的段的延迟时间，从而防止缓冲器溢出; 并且，该系统还允许具有低负载的VoQ在没有高负载的VoQ的影响下传输段，并且刚刚读出该段。
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公开(公告)号：US20060077915A1
公开(公告)日：2006-04-13
申请号：US11020484
申请日：2004-12-27
申请人： Masayuki Takase , Minoru Hidaka , Takeki Yazaki , Tomoyuki Oku
发明人： Masayuki Takase , Minoru Hidaka , Takeki Yazaki , Tomoyuki Oku
IPC分类号： H04L5/22
摘要： To control a bandwidth without the need for a large-capacity buffer. This invention provides a packet transfer apparatus connected to first device and second device, with a network therebetween, including: an input unit that receives a packet from the first device; a packet storage unit that stores the packet; a packet processing unit that stores the packet in the packet storage unit; a packet checking unit that checks whether the packet is related to data request; a packet analyzing unit that analyzes the amount of data requested by the data request; a transfer control unit that controls transfer of the packet on the basis of the analyzed amount of data; and an output unit that sends the received packet to the second device.
摘要翻译： 控制带宽，无需大容量缓冲区。 本发明提供了一种连接到第一设备和第二设备的分组传送设备，其间具有网络，包括：输入单元，其从第一设备接收分组; 存储分组的分组存储单元; 分组处理单元，其将分组存储在分组存储单元中; 分组检查单元，检查分组是否与数据请求相关; 分组分析单元，其分析由所述数据请求请求的数据量; 传送控制单元，其基于分析的数据量来控制分组的传送; 以及将接收到的分组发送到第二设备的输出单元。
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公开(公告)号：US06999413B2
公开(公告)日：2006-02-14
申请号：US09940476
申请日：2001-08-29
IPC分类号： G01R31/08
CPC分类号： H04L49/101 , H04L49/1523 , H04L49/1576 , H04L49/3027 , H04L49/3045 , H04L49/3072 , H04L49/45
摘要： A packet switch has a switch section formed by a plurality of crossbar switch planes and plurality of interfaces, and each interface outputs in parallel input packets in block units to the plurality of crossbar switch planes in response to signals from a scheduler, wherein when n crossbar switch planes can be mounted on the packet switch, each interface allocates time slots corresponding to the n crossbar switch planes or when a switch plane is additionally mounted, a block is read at a time slot corresponding to the additional switch plane or when a switch plane is stopped from working, an idle time slot is used to prevent a block from being output to the switch plane which is unused.
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公开(公告)号：US20050157752A1
公开(公告)日：2005-07-21
申请号：US10889139
申请日：2004-07-13
申请人： Masayuki Takase , Takeki Yazaki
发明人： Masayuki Takase , Takeki Yazaki
IPC分类号： H04L12/815 , H04L12/829 , H04L12/863 , H04L12/951 , H04L29/08 , H04L12/56
CPC分类号： H04L49/205 , H04L49/35 , H04L67/1097 , H04L69/329
摘要： A storage switch with bandwidth control function for preventing discarding of packets for bandwidth breach when sending or receiving storage data using an iSCSI protocol on a wide area network having a covenant (guaranteed) bandwidth, when the quantity of storage data traffic sent by the initiator or target was judged a bandwidth breach or violation. The traffic amount is predicted from the Expected Data Transfer Length contained in the read request of the iSCSI command and the Desired Data Transfer Length contained in the R2T command, when that command is sent to the target and the initiator and the bandwidth is regulated by controlling the transmission timing of that command.
摘要翻译： 具有带宽控制功能的存储交换机，用于在发起或接收存储数据时使用iSCSI协议在具有契约（保证）带宽的广域网上发送或接收存储数据时防止数据包丢弃，当启动器发送的存储数据流量或 目标被判定为带宽违规或违规。 根据iSCSI命令的读取请求中包含的预期数据传输长度和R2T命令中包含的期望数据传输长度来预测流量，当该命令发送到目标端并且启动器和带宽被控制时 该命令的发送定时。
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公开(公告)号：US08711258B2
公开(公告)日：2014-04-29
申请号：US13428024
申请日：2012-03-23
IPC分类号： H04N3/14 , H04N5/225 , H01L31/062 , H01L27/00
CPC分类号： G02B3/0068 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14685
摘要： A solid-state imaging device includes a semiconductor substrate having a plurality of light-receiving portions (PD) formed therein, a wiring layer formed on the semiconductor substrate, color filters formed on the wiring layer in a manner individually corresponding to the light-receiving portions (PD) of the semiconductor substrate, and partition walls each formed between the individual color filters. Each of the partition walls includes a lower layer portion and an upper layer portion, an upper surface of the lower layer portion is modified into a modified layer, and an interface for facilitating reflection of penetration light from outside is structured between the modified layer and the upper layer portion.
摘要翻译： 一种固体摄像器件包括：具有形成在其中的多个受光部（PD）的半导体衬底;形成在半导体衬底上的布线层，以与光接收相对应的方式形成在布线层上的滤色器 半导体衬底的部分（PD）和各个滤色器之间形成的间隔壁。 每个分隔壁包括下层部分和上层部分，下层部分的上表面被修改为改性层，并且在改性层和改性层之间构成用于促进穿透光反射的界面 上层部分。
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