公开(公告)号：US07502275B2

公开(公告)日：2009-03-10

申请号：US11438668

申请日：2006-05-23

申请人： Koji Nii ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

发明人： Koji Nii ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

IPC分类号： G11C5/14

CPC分类号： G11C11/419 ,  G11C5/063 ,  G11C11/412

摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

摘要翻译： 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

公开(公告)号：US20060262628A1

公开(公告)日：2006-11-23

申请号：US11438668

申请日：2006-05-23

申请人： Koji Nii ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

发明人： Koji Nii ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

IPC分类号： G11C5/14

CPC分类号： G11C11/419 ,  G11C5/063 ,  G11C11/412

摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

公开(公告)号：US5051948A

公开(公告)日：1991-09-24

申请号：US434692

申请日：1989-10-20

申请人： Kiyoto Watabe ,  Hirofumi Shinohara ,  Takahisa Eimori ,  Hideaki Arima ,  Natsuo Ajika ,  Yuichi Nakashima ,  Shinichi Satoh

发明人： Kiyoto Watabe ,  Hirofumi Shinohara ,  Takahisa Eimori ,  Hideaki Arima ,  Natsuo Ajika ,  Yuichi Nakashima ,  Shinichi Satoh

IPC分类号： G11C15/04

CPC分类号： G11C15/046

摘要： In a content addressable memory (CAM) cell according to the present invention, a pair of non-volatile memory transistors hold data, whereby stored data will not disappear even if power is cut. Conducting terminals of these non-volatile transistors are connected to a bit line pair, so that the stored data can be directly read out from the bit line pair. Further, the invention CAM system converts the value of a current flowing in a match line into a voltage value to perform content reference, and hence the same can be employed as an associative memory system.

摘要翻译： PCT No.PCT / JP89 / 00179 Sec。 371日期1989年10月20日第 102（e）日期1989年10月20日PCT提交1989年2月22日PCT公布。 出版物WO89 / 08314 日本1989年9月8日。在根据本发明的内容可寻址存储器（CAM）单元中，一对非易失性存储晶体管保持数据，由此即使切断功率，存储的数据也不会消失。 这些非易失性晶体管的导通端子连接到位线对，从而可以从位线对直接读出所存储的数据。 此外，本发明CAM系统将在匹配线中流动的电流的值转换为电压值以执行内容参考，因此可以将其用作关联存储器系统。

公开(公告)号：US4893282A

公开(公告)日：1990-01-09

申请号：US133153

申请日：1987-12-07

申请人： Tomohisa Wada ,  Hirofumi Shinohara

发明人： Tomohisa Wada ,  Hirofumi Shinohara

IPC分类号： G11C7/00 ,  G11C8/18 ,  G11C11/41

CPC分类号： G11C8/18

摘要： In a semiconductor memory device in accordance with the present invention, a plurality of address signals (A.sub.1 to A.sub.N) are applied to address transition detection (ATD) circuits (31 to 3N) through input buffers (11 to 1N) and according to a level change in the address signals, a pulse signal (ATDi) is applied to an inverter (5) through any of MOS field-effect transistors (41 to 4N). The input level of the inverter (5) falls rapidly in response to the rise of the output level of the ATD circuits (31 to 3N) and rises slowly by the influence of a load device (40). A chip select transition detection (CSTD) circuit (6) generates a pulse signal (CST) in response to the change from a high level to a low level of a chip selection signal (CS) provided from a CS buffer (2). In response to the pulse signal (CST), a p channel MOS field-effect transistor (71) is turned on and a load device (72) is connected between the power supply potential and the input of the inverter (5). As a result, the impedance therebetween is lowered and an ATD signal rises rapidly. Thus, a delay with respect to the access by the address signals can be prevented.

摘要翻译： 在根据本发明的半导体存储器件中，通过输入缓冲器（11至1N）将多个地址信号（A1至AN）施加到地址转换检测（ATD）电路（31至3N），并根据电平 改变地址信号，脉冲信号（ATDi）通过MOS场效应晶体管（41〜4N）中的任何一个施加到逆变器（5）。 逆变器（5）的输入电平响应于ATD电路（31至3N）的输出电平的升高而迅速下降，并且由于负载装置（40）的影响而缓慢上升。 芯片选择转换检测（CSTD）电路（6）响应于从CS缓冲器（2）提供的芯片选择信号（CS）的高电平到低电平的变化产生脉冲信号（＆amp; upbar＆amp; C）。 响应于脉冲信号（＆amp; amp＆amp; C），p沟道MOS场效应晶体管（71）导通，并且负载装置（72）连接在电源电位和反相器（5）的输入端之间。 结果，它们之间的阻抗降低，并且ATD信号迅速上升。 因此，可以防止相对于地址信号的访问的延迟。

公开(公告)号：US4645998A

公开(公告)日：1987-02-24

申请号：US770426

申请日：1985-08-29

申请人： Hirofumi Shinohara ,  Katsuki Ichinose

发明人： Hirofumi Shinohara ,  Katsuki Ichinose

IPC分类号： G05F3/24 ,  G05F3/20

CPC分类号： G05F3/247

摘要： A constant voltage generating circuit comprises a power supply terminal (1), an output terminal (2), a p-channel MOS FET (3), n-channel MOS FET's (4 and 5) and resistors (8 and 9). A node C of the resistors (8) and (9) is connected to a control terminal of the n-channel MOS FET (4), whereby the potential in the output terminal (2) is determined mainly by the threshold voltage of the n-channel MOS FETs (4) and (5), a ratio of the resistance values of the resistors (8) and (9) and a degree of conduction of the n-channel MOS FET (4). Instead of the resistors (8) and (9), n-channel MOS FET's (10 and 11) may be provided so as to compensate for the influence of power supply voltage in the output voltage by changing the impedance of the n-channel MOS FET (10) according to the change of the voltage of the power supply terminal (1).

摘要翻译： 恒压生成电路包括电源端子（1），输出端子（2），p沟道MOS FET（3），n沟道MOS FET（4和5）和电阻器（8和9）。 电阻器（8）和（9）的节点C连接到n沟道MOS FET（4）的控制端子，由此输出端子（2）中的电位主要由n的阈值电压 沟道MOS FET（4）和（5），电阻器（8）和（9）的电阻值与n沟道MOS FET（4）的导通率之比。 代替电阻器（8）和（9），可以提供n沟道MOS FET（10和11），以通过改变n沟道MOS的阻抗来补偿输出电压中的电源电压的影响 FET（10）根据电源端子（1）的电压变化。