公开(公告)号：US06617666B2

公开(公告)日：2003-09-09

申请号：US10093114

申请日：2002-03-07

申请人： Takashi Yoshitomi ,  Yuichi Nakashima

发明人： Takashi Yoshitomi ,  Yuichi Nakashima

IPC分类号： H01L2900

CPC分类号： H01L28/40 ,  H01L21/31116 ,  H01L21/31604 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76834 ,  Y10S438/957

摘要： A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.

公开(公告)号：US5204540A

公开(公告)日：1993-04-20

申请号：US673655

申请日：1991-03-21

申请人： Yuichi Nakashima ,  Shintaro Matsuda

发明人： Yuichi Nakashima ,  Shintaro Matsuda

IPC分类号： H01L21/56 ,  H01L21/66 ,  H01L23/28 ,  H01L23/544

CPC分类号： H01L22/34 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181

摘要： A resin sealed semiconductor device for use in testing is disclosed, in which a first MOS field effect transistor is formed in a region within 100 .mu.m from an outer perimeter of a main surface of a silicon substrate, and a second MOS field effect transistor is formed in a region 100 .mu.m or more distant from an outer perimeter of the main surface, and the first and second MOS field effect transistors are encapsulated with resin. Dimensions and materials of the first MOS field effect transistor and the second MOS field effect transistor are identical. By comparing the electric characteristics of the first MOS field effect transistor and the electric characteristics of the second MOS field effect transistor, the effect produced on the MOS field effect transistors by the mechanical stresses due to the resin seal applied from a side direction of silicon substrate can be evaluated.

摘要翻译： 公开了一种用于测试的树脂密封半导体器件，其中第一MOS场效应晶体管形成在距离硅衬底的主表面的外周边100μm以内的区域中，第二MOS场效应晶体管是 形成在远离主表面的外周边100μm或更远的区域中，第一和第二MOS场效应晶体管被树脂封装。 第一MOS场效应晶体管和第二MOS场效应晶体管的尺寸和材料相同。 通过比较第一MOS场效应晶体管的电特性和第二MOS场效应晶体管的电特性，通过由硅衬底的侧面方向施加的树脂密封的机械应力对M​​OS场效应晶体管产生的影响 可以评估。

公开(公告)号：US07268434B2

公开(公告)日：2007-09-11

申请号：US11397707

申请日：2006-04-05

申请人： Yuichi Nakashima

发明人： Yuichi Nakashima

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/7681 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is disclosed a semiconductor device comprising at least one first insulating film provided above a substrate, being formed with at least one first recess having a first width, and being formed with at least one second recess having a second width which is 1/x (x: positive numbers larger than 1) a size of the first width and having a same depth as the first recess, a second insulating film provided at both sides of the first recess and at a lower part of the second recess, and a conductor provided inside of the second insulating films provided at the both sides of the first recess with extending from an opening of the first recess to a bottom surface thereof, and provided with extending from an opening of the second recess to an upper surface of the second insulating film provided at the lower part of the second recess.

摘要翻译： 公开了一种半导体器件，其包括设置在衬底上方的至少一个第一绝缘膜，形成有至少一个具有第一宽度的第一凹部，并且形成有至少一个具有第二宽度的第二凹槽，该第二凹槽为1 / x（ x：大于1的正数）第一宽度的尺寸并且具有与第一凹部相同的深度;第二绝缘膜，设置在第一凹部的两侧和第二凹部的下部;以及导体， 设置在第一凹部的两侧的第二绝缘膜的内部从第一凹部的开口延伸到其底表面，并且设置有从第二凹部的开口延伸到第二绝缘膜的上表面 设置在第二凹部的下部。

公开(公告)号：US07242094B2

公开(公告)日：2007-07-10

申请号：US10626592

申请日：2003-07-25

申请人： Takeshi Matsunaga ,  Yuichi Nakashima ,  Koji Miyamoto

发明人： Takeshi Matsunaga ,  Yuichi Nakashima ,  Koji Miyamoto

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L28/40 ,  H01L21/76838 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.

摘要翻译： 一种具有形成在多层布线结构中的电容器的半导体器件，所述半导体器件包括多层布线结构，所述多层布线结构包括形成在基板上的多个布线层，布置在所述多层布线结构中的预定布线层中并具有下电极 介电膜和上电极，形成在预定布线层中并连接到电容器的上电极的顶表面的第一通孔，以及形成在叠置在预定布线层上的上覆布线层中的第二通孔， 第二通孔形成在第一通孔上。

公开(公告)号：US6004840A

公开(公告)日：1999-12-21

申请号：US744524

申请日：1996-11-06

申请人： Koji Kimura ,  Yuichi Nakashima ,  Hiroshi Kawamoto

发明人： Koji Kimura ,  Yuichi Nakashima ,  Hiroshi Kawamoto

IPC分类号： H01L21/768 ,  H01L21/8249

CPC分类号： H01L21/76895 ,  H01L21/8249

摘要： In a semiconductor device, a first conductive film made of, for example, polysilicon is formed on the element region of the semiconductor substrate. An insulation film is formed on the semiconductor substrate, for covering at least the first conductive film. A second conductive film covers at least the end portion of the insulation film. The first conductive film is used as a gate electrode of the MOS transistor, and the second conductive film is used as a protection film for covering and protecting the end portion of the insulation film and a lead-out electrode of the bipolar transistor. The end portion of the insulation film is covered and protected by the second conductive film obtained by patterning the conductive layer made of, for example, polysilicon. Further, the conductive layer is patterned so that stepped portions formed on the insulation film and the end portion of the insulation film are covered, and using this pattern, anisotropic etching is carried out. Thus, formation of residue on the side-wall of the second conductive film, on the stepped portions formed as covering the first conductive film, can be avoided. In a later step, the pattern of the second conductive film which covers the stepped portion is removed by etching.

摘要翻译： 在半导体器件中，在半导体衬底的元件区域上形成由例如多晶硅制成的第一导电膜。 绝缘膜形成在半导体衬底上，用于至少覆盖第一导电膜。 第二导电膜至少覆盖绝缘膜的端部。 第一导电膜用作MOS晶体管的栅电极，第二导电膜用作覆盖和保护绝缘膜的端部和双极晶体管的引出电极的保护膜。 绝缘膜的端部由通过图案化例如由多晶硅制成的导电层获得的第二导电膜覆盖和保护。 此外，导电层被图案化，使得形成在绝缘膜上的阶梯部分和绝缘膜的端部被覆盖，并且使用该图案进行各向异性蚀刻。 因此，可以避免在形成为覆盖第一导电膜的阶梯部分上在第二导电膜的侧壁上形成残留物。 在后续步骤中，通过蚀刻去除覆盖阶梯部分的第二导电膜的图案。

公开(公告)号：US5877067A

公开(公告)日：1999-03-02

申请号：US839168

申请日：1997-04-23

申请人： Koji Kimura ,  Rintarou Okamoto ,  Yuichi Nakashima

发明人： Koji Kimura ,  Rintarou Okamoto ,  Yuichi Nakashima

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/06

CPC分类号： H01L21/763 ,  Y10S148/05

摘要： The present invention provides a method of manufacturing a semiconductor device to prevent the generation of crystalline defects due to shorting between interconnects resulting from etch residue as a result of the generation of vertical bird's beaks on top of the trench during field oxidation layer formation. The method includes forming an epitaxial layer over a semiconductor substrate, depositing a first SiO.sub.2 layer, an SiN layer and a second SiO.sub.2 layer in that order upon said epitaxial layer and forming a trench from the second SiO.sub.2 layer extending into the semiconductor substrate. A third SiO.sub.2 layer is formed coating said trench with a region of said third Si0.sub.2 layer removed adjacent to said first SiO.sub.2 layer to expose a portion of said epitaxial layer within said trench. The trench is then filled with a first polysilicon layer to coat the third SiO.sub.2 layer and the first SiO.sub.2 layer followed by removal of the second SiO.sub.2 layer and the SiN layer and finally, the first SiO.sub.2 layer is oxidized to a depth extending into the trench corresponding to the exposed portion of the epitaxial layer so as to form a field oxide layer.

摘要翻译： 本发明提供了一种制造半导体器件的方法，以防止由于在场氧化层形成期间在沟槽顶部产生垂直鸟嘴而导致的由蚀刻残留导致的互连之间的短路而产生晶体缺陷。 该方法包括在半导体衬底上形成外延层，在所述外延层上依次沉积第一SiO 2层，SiN层和第二SiO 2层，并从延伸到半导体衬底中的第二SiO 2层形成沟槽。 形成第三SiO 2层，所述沟槽的所述第三SiO 2层的区域与所述第一SiO 2层相邻地去除，以暴露所述沟槽内的所述外延层的一部分。 然后用第一多晶硅层填充沟槽，以涂覆第三SiO 2层和第一SiO 2层，随后除去第二SiO 2层和SiN层，最后，第一SiO 2层被氧化成延伸到沟槽对应的深度 到外延层的暴露部分以形成场氧化物层。

公开(公告)号：US06864137B2

公开(公告)日：2005-03-08

申请号：US10619394

申请日：2003-07-15

申请人： Takashi Yoshitomi ,  Yuichi Nakashima

发明人： Takashi Yoshitomi ,  Yuichi Nakashima

IPC分类号： H01L23/52 ,  H01L21/02 ,  H01L21/304 ,  H01L21/311 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04 ,  H01L21/8242

CPC分类号： H01L28/40 ,  H01L21/31116 ,  H01L21/31604 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76834 ,  Y10S438/957

摘要： A process of manufacturing a semiconductor device. The initial process steps are forming a first insulating film above a semiconductor substrate and removing a selected portion of the first insulating film to form an opening. The next step is depositing a first electrode, a dielectric film and a second electrode successively on a bottom portion of the opening, The deposits being oriented such that they are in substantially parallel relationship with a surface of the semiconductor substrate. The final steps are removing selected portions of the first electrode, the dielectric film and the second electrode, forming a capacitor at a selected position in the opening, forming a second insulating film at least in the opening, and forming a third insulating film on the second insulating film.

摘要翻译： 一种制造半导体器件的工艺。 初始工艺步骤是在半导体衬底上形成第一绝缘膜，并去除第一绝缘膜的选定部分以形成开口。 下一步是在开口的底部依次沉积第一电极，电介质膜和第二电极。沉积物取向为使得它们与半导体衬底的表面基本平行。 最后的步骤是去除第一电极，电介质膜和第二电极的选定部分，在开口中的选定位置形成电容器，至少在开口中形成第二绝缘膜，并在第二绝缘膜上形成第三绝缘膜 第二绝缘膜。

公开(公告)号：US5604371A

公开(公告)日：1997-02-18

申请号：US421795

申请日：1995-04-14

申请人： Koji Kimura ,  Yuichi Nakashima ,  Hiroshi Kawamoto

发明人： Koji Kimura ,  Yuichi Nakashima ,  Hiroshi Kawamoto

IPC分类号： H01L21/768 ,  H01L21/8249 ,  H01L29/41

CPC分类号： H01L21/8249 ,  H01L21/76895

摘要： In a semiconductor device, a first conductive film made of, for example, polysilicon is formed on the element region of the semiconductor substrate. An insulation film is formed on the semiconductor substrate, for covering at least the first conductive film. A second conductive film covers at least the end portion of the insulation film. The first conductive film is used as a gate electrode of the MOS transistor, and the second conductive film is used as a protection film for covering and protecting the end portion of the insulation film and a lead-out electrode of the bipolar transistor. The end portion of the insulation film is covered and protected by the second conductive film obtained by patterning the conductive layer made of, for example, polysilicon. Further, the conductive layer is patterned so that stepped portions formed on the insulation film and the end portion of the insulation film are covered, and using this pattern, anisotropic etching is carried out. Thus, formation of residue on the side-wall of the second conductive film, on the stepped portions formed as covering the first conductive film, can be avoided. In a later step, the pattern of the second conductive film which covers the stepped portion is removed by etching.

摘要翻译： 在半导体器件中，在半导体衬底的元件区域上形成由例如多晶硅制成的第一导电膜。 绝缘膜形成在半导体衬底上，用于至少覆盖第一导电膜。 第二导电膜至少覆盖绝缘膜的端部。 第一导电膜用作MOS晶体管的栅电极，第二导电膜用作覆盖和保护绝缘膜的端部和双极晶体管的引出电极的保护膜。 绝缘膜的端部由通过图案化例如由多晶硅制成的导电层获得的第二导电膜覆盖和保护。 此外，导电层被图案化，使得形成在绝缘膜上的阶梯部分和绝缘膜的端部被覆盖，并且使用该图案进行各向异性蚀刻。 因此，可以避免在形成为覆盖第一导电膜的阶梯部分上在第二导电膜的侧壁上形成残留物。 在后续步骤中，通过蚀刻去除覆盖阶梯部分的第二导电膜的图案。

公开(公告)号：US5051948A

公开(公告)日：1991-09-24

申请号：US434692

申请日：1989-10-20

申请人： Kiyoto Watabe ,  Hirofumi Shinohara ,  Takahisa Eimori ,  Hideaki Arima ,  Natsuo Ajika ,  Yuichi Nakashima ,  Shinichi Satoh

发明人： Kiyoto Watabe ,  Hirofumi Shinohara ,  Takahisa Eimori ,  Hideaki Arima ,  Natsuo Ajika ,  Yuichi Nakashima ,  Shinichi Satoh

IPC分类号： G11C15/04

CPC分类号： G11C15/046

摘要： In a content addressable memory (CAM) cell according to the present invention, a pair of non-volatile memory transistors hold data, whereby stored data will not disappear even if power is cut. Conducting terminals of these non-volatile transistors are connected to a bit line pair, so that the stored data can be directly read out from the bit line pair. Further, the invention CAM system converts the value of a current flowing in a match line into a voltage value to perform content reference, and hence the same can be employed as an associative memory system.

摘要翻译： PCT No.PCT / JP89 / 00179 Sec。 371日期1989年10月20日第 102（e）日期1989年10月20日PCT提交1989年2月22日PCT公布。 出版物WO89 / 08314 日本1989年9月8日。在根据本发明的内容可寻址存储器（CAM）单元中，一对非易失性存储晶体管保持数据，由此即使切断功率，存储的数据也不会消失。 这些非易失性晶体管的导通端子连接到位线对，从而可以从位线对直接读出所存储的数据。 此外，本发明CAM系统将在匹配线中流动的电流的值转换为电压值以执行内容参考，因此可以将其用作关联存储器系统。

公开(公告)号：US20070032067A1

公开(公告)日：2007-02-08

申请号：US11397707

申请日：2006-04-05

申请人： Yuichi Nakashima

发明人： Yuichi Nakashima

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/7681 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is disclosed a semiconductor device comprising at least one first insulating film provided above a substrate, being formed with at least one first recess having a first width, and being formed with at least one second recess having a second width which is 1/x (x: positive numbers larger than 1) a size of the first width and having a same depth as the first recess, a second insulating film provided at both sides of the first recess and at a lower part of the second recess, and a conductor provided inside of the second insulating films provided at the both sides of the first recess with extending from an opening of the first recess to a bottom surface thereof, and provided with extending from an opening of the second recess to an upper surface of the second insulating film provided at the lower part of the second recess.