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95 条记录 (耗时 0.04 秒)

    Nonvolatile semiconductor memory device and its manufacture
    42.
    发明授权
    Nonvolatile semiconductor memory device and its manufacture 有权
    非易失性半导体存储器件及其制造

    公开(公告)号：US06274907B1

    公开(公告)日：2001-08-14

    申请号：US09454996

    申请日：1999-12-06

    申请人： Shinichi Nakagawa

    发明人： Shinichi Nakagawa

    IPC分类号： H01L310392

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： On a SIMOX substrate having a plurality of STI layers and first conductivity type semiconductor layers disposed in the row direction, a stacked-layer structure SS is formed on a gate dielectric film formed on the first conductivity type semiconductor layer, the structure SS being made of a first polysilicon film, a second gate dielectric film and a second polysilicon film. Second conductivity type source and drain regions are formed in the first conductivity type semiconductor layer on both sides of the structure SS. In a plurality of source regions adjacent in the column direction between the stacked-layer structures SS, a common source line CSL is formed which is made of second conductivity type source region connecting semiconductor regions, source regions and conductive films formed on these semiconductor and source regions.

    摘要翻译： 在具有排列在行方向上的多个STI层和第一导电型半导体层的SIMOX基板上，在形成于第一导电型半导体层上的栅极电介质膜上形成层叠结构SS，其结构SS由 第一多晶硅膜，第二栅极介电膜和第二多晶硅膜。 在结构SS的两侧的第一导电型半导体层中形成第二导电型源极和漏极区。 在堆叠层结构SS之间的列方向上相邻的多个源极区域中，形成公共源极线CSL，该源极线CSL由连接半导体区域的第二导电型源极区域，形成在这些半导体和源极上的源极区域和导电膜 地区。

    Operational amplifier
    43.
    发明授权
    Operational amplifier 失效
    运算放大器

    公开(公告)号：US6163217A

    公开(公告)日：2000-12-19

    申请号：US292935

    申请日：1999-04-16

    申请人： Kunihiro Matsubara ,  Hidenobu Ito ,  Shinichi Nakagawa

    发明人： Kunihiro Matsubara ,  Hidenobu Ito ,  Shinichi Nakagawa

    IPC分类号： H03F1/32 ,  H03F1/34 ,  H03F3/30 ,  H03F3/45

    CPC分类号： H03F3/3023 ,  H03F3/45183 ,  H03F2203/30021 ,  H03F2203/30036 ,  H03F2203/45508 ,  H03F2203/45658

    摘要： A current charged into or discharged from a phase-compensating capacitor C1 in an output circuit is controlled by a level shift circuit so that the current is kept constant for input signals inputted to the input terminals IN+ and IN- of a differential amplifier circuit, and also a current charged into or discharged from a phase-compensating capacitor C2 is controlled by the current correcting circuit so that the current become equal to a constant current controlled by the level shift circuit, namely to a current charged into or discharged from the phase-compensating capacitor C1. Therefore, even if a quickly rising or falling signal is inputted into the differential amplifier circuit, the MOS transistor MP11 or MN11 is not set in an offset state, which prevents generation of an overshoot or an undershot in the output terminal.

    摘要翻译： 通过电平移位电路来控制在输出电路中充入或从相位补偿电容器C1放电的电流，使得电流对于输入到差分放大器电路的输入端IN +和IN-的输入信号保持恒定，以及 另外，由电流校正电路控制充电到相位补偿电容器C2的放电电流，也可以由电平移位电路控制的电流变为等于从相位补偿电容器C2充放电的电流， 补偿电容器C1。 因此，即使快速上升或下降信号被输入到差分放大器电路中，MOS晶体管MP11或MN11也不被设置在偏移状态，这防止了在输出端子中产生过冲或欠压。

    Program execution control device having addressability in accordance with M series pseudo-random number sequence
    45.
    发明授权
    Program execution control device having addressability in accordance with M series pseudo-random number sequence 失效
    具有符合M系列伪随机数序列的寻址能力的程序执行控制装置

    公开(公告)号：US5651123A

    公开(公告)日：1997-07-22

    申请号：US460947

    申请日：1995-06-05

    申请人： Shinichi Nakagawa ,  Kazuya Ishihara ,  Satoshi Kumaki ,  Atsuo Hanami ,  Hiroshi Segawa ,  Tetsuya Matsumura

    发明人： Shinichi Nakagawa ,  Kazuya Ishihara ,  Satoshi Kumaki ,  Atsuo Hanami ,  Hiroshi Segawa ,  Tetsuya Matsumura

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3802 ,  G06F9/321 ,  G06F2207/7219

    摘要： Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.

    摘要翻译： 程序的指令按照程序地址的顺序存储在指令存储器中根据M系列伪随机数序列顺序指定的地址处。 伪随机数程序计数器具有用于产生相同M系列伪随机数序列的反馈移位寄存器，并且基于生成的伪随机数将从指令存储器读出的指令的地址应用于指令存储器， 以及来自指令解码器的跳转地址和选择信号。 结果，从指令存储器中读取指令并按程序地址的顺序执行。 反馈移位寄存器可以实现为小规模电路并且可以高速运行。

    Semiconductor integrated circuit device and semiconductor memory device
    46.
    发明授权
    Semiconductor integrated circuit device and semiconductor memory device 失效
    半导体集成电路器件和半导体存储器件

    公开(公告)号：US5479369A

    公开(公告)日：1995-12-26

    申请号：US375877

    申请日：1995-01-20

    申请人： Tetsuya Matsumura ,  Satoshi Kumaki ,  Shinichi Nakagawa

    发明人： Tetsuya Matsumura ,  Satoshi Kumaki ,  Shinichi Nakagawa

    IPC分类号： G11C11/417 ,  G11C7/10 ,  H01L27/10 ,  H03K3/356 ,  G11C7/00

    CPC分类号： H03K3/356173 ,  G11C7/1051 ,  H03K3/356121

    摘要： In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

    摘要翻译： 在具有数据锁存功能的半导体集成电路器件中，构成数据锁存电路的两个反相器中的一个由PMOS晶体管和NMOS晶体管构成，NMOS晶体管的源极端子连接到用于施加复位信号的端子 。 复位信号通过NMOS晶体管施加到逆变器，反相器反相复位信号并复位数据锁存电路。 由于数据锁存电路的一个反相器由PMOS晶体管和NMOS晶体管形成，因此可以容易地实现半导体集成电路器件的设置/复位功能。

    Layout designing method for a semiconductor integrated circuit device
    47.
    发明授权
    Layout designing method for a semiconductor integrated circuit device 失效
    半导体集成电路器件的布局设计方法

    公开(公告)号：US5365454A

    公开(公告)日：1994-11-15

    申请号：US777704

    申请日：1991-10-17

    申请人： Shinichi Nakagawa ,  Hiroyuki Kawai

    发明人： Shinichi Nakagawa ,  Hiroyuki Kawai

    IPC分类号： H01L21/82 ,  G06F17/50 ,  H01L27/118 ,  G06F15/60

    CPC分类号： G06F17/5068 ,  H01L27/11807

    摘要： In a layout designing method for an LSI by a CMOS standard cell method, layout cells (standard layout patterns) which respectively correspond to logical function units are selected from a library. In this selection, the respective layout cells are selected from the library as patterns which are divided into p-type layout cells and n-type layout cells. The p-type layout cells and the n-type layout cells are arranged in accordance with a predetermined logical circuit diagram. Interconnection patterns for interconnecting the p-type layout cells and for interconnecting the n-type layout cells are arranged in accordance with the logical circuit diagram. An excessive interconnection region can be minimized, and efficient interconnections can be achieved. Therefore, an occupied plane area can be reduced in the layout design.

    摘要翻译： 在通过CMOS标准单元方法的LSI的布局设计方法中，从库中选择分别对应于逻辑功能单元的布局单元（标准布局图案）。 在该选择中，将各个布局单元从库中选择为分为p型布局单元和n型布局单元的图案。 p型布局单元和n型布局单元根据预定的逻辑电路图布置。 用于互连p型布局单元和用于互连n型布局单元的互连模式根据逻辑电路图布置。 可以最小化过度的互连区域，并且可以实现有效的互连。 因此，布局设计中可以减少占用面积。

    Variable direction filter for separation of luminance and chrominance signals
    48.
    发明授权
    Variable direction filter for separation of luminance and chrominance signals 失效
    用于分离亮度和色度信号的可变方向滤波器

    公开(公告)号：US4727415A

    公开(公告)日：1988-02-23

    申请号：US783536

    申请日：1985-10-03

    申请人： Shinichi Nakagawa ,  Tokumichi Murakami

    发明人： Shinichi Nakagawa ,  Tokumichi Murakami

    IPC分类号： H04N9/78 ,  H04N9/64

    CPC分类号： H04N9/78

    摘要： Signal generating means formed by variable line delay circuits 6 and 9 and dot delay circuits 7 and 8 receives a series of signal sample of a composite color television signal sampled in synchronism with a chrominance subcarrier at a frequency four times the chrominance subcarrier frequency and generates simultaneously a sample signal at a specified sampled point for separating a luminance signal and a chrominance signal and sampled signals at four sample points adjacent to the specified sample point, namely, four sampled points on the upper, lower, right and left sides of the specified sample point. A comparing and determining circuit 10 compares and determines a direction in which there is little change in the picture, based on the sampled signals at the adjacent sample points. Based on the result of determination of the comparing and determining circuit 10, a selector 11 selects and provides two sampled signals 110 and 111 existing in a region where there is little change in the picture. A separation filter 12 separates a chrominance signal 105 from the sampled signal 102 at the specified sample point using the two sampled signals 110 and 111 provided from the selector 11. A subtractor 5 subtracts the chrominance signal 105 from the sampled signal 102 at the specified sample point so as to provide a luminance signal 106.

    摘要翻译： 由可变行延迟电路6和9以及点延迟电路7和8形成的信号产生装置接收与色度副载波频率采样的复合彩色电视信号的一系列信号样本，其频率为色度副载波频率的四倍，同时产生 用于分离亮度信号和色度信号的指定采样点的采样信号以及与指定采样点相邻的四个采样点处的采样信号，即在指定采样的上，下，右和左侧上的四个采样点 点。 比较和确定电路10基于相邻采样点处的采样信号来比较并确定图像中几乎没有变化的方向。 基于比较和确定电路10的确定结果，选择器11选择并提供存在于图像变化不大的区域中的两个采样信号110和111。 分离滤波器12使用从选择器11提供的两个采样信号110和111，在指定的采样点处将色度信号105与采样信号102分离。减法器5从指定采样的采样信号102中减去色度信号105 以便提供亮度信号106。

    Fluorine-containing copolymer
    49.
    发明授权
    Fluorine-containing copolymer 失效
    含氟共聚物

    公开(公告)号：US4703095A

    公开(公告)日：1987-10-27

    申请号：US829221

    申请日：1986-02-14

    申请人： Shinichi Nakagawa ,  Tsuneo Nakagawa ,  Toshihiko Amano ,  Mitsugu Omori ,  Sadaatsu Yamaguchi ,  Kozo Asano

    发明人： Shinichi Nakagawa ,  Tsuneo Nakagawa ,  Toshihiko Amano ,  Mitsugu Omori ,  Sadaatsu Yamaguchi ,  Kozo Asano

    IPC分类号： C08F214/26 ,  C08F16/24

    CPC分类号： C08F214/262

    摘要： A fluorine-containing copolymer comprising monomeric units of:(a) tetrafluoroethylene,(b) 8 to 15% by weight of hexafluoropropene on the basis of the weight of the copolymer, and(c) 0.2 to 2% by weight of a fluoroalkyl vinyl ether of the formula:CF.sub.2 .dbd.CF--O--(CF.sub.2).sub.n --CF.sub.2 X wherein X is hydrogen or fluorine, and n is an integer of 3 to 9, on the basis of the weight of the copolymer, which has good moldability and improved stress crack resistance and flex resistance when formed as an article such as a film.

    摘要翻译： 一种含氟共聚物，其包含单体单元：（a）四氟乙烯，（b）基于共聚物重量的8至15重量％的六氟丙烯，和（c）0.2至2重量％的氟代烷基乙烯基 醚：式中X为氢或氟的CF 2 = CF-O-（CF 2）n -CF 2 X，n为3〜9的整数，基于共聚物的重量，其成型性良好且改善 当作为诸如膜的物品形成时的抗应力开裂性和抗挠曲性。