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    Clock generator which generates a non-overlap clock having fixed pulse width and changeable frequency
    1.
    发明授权
    Clock generator which generates a non-overlap clock having fixed pulse width and changeable frequency 失效
    时钟发生器，其产生具有固定脉冲宽度和可变频率的非重叠时钟

    公开(公告)号：US4877974A

    公开(公告)日：1989-10-31

    申请号：US189885

    申请日：1988-05-03

    申请人： Hiroyuki Kawai ,  Shinichi Nakagawa

    发明人： Hiroyuki Kawai ,  Shinichi Nakagawa

    IPC分类号： G06F1/06 ,  H03K5/15

    CPC分类号： H03K5/1502 ,  H03K5/15033

    摘要： A clock generator which is cascade connected a plurality of single-phase pulse generator circuits including RS flip-flops and delay circuits for defining the pulse width of one output at the RS flip-flop through gates controlling propagation of the other output of the RS flip-flop, so that the final clock frequency is variable by switching control of each gate, whereby a pulse width of each single-phase clock is defined by a delay duration of a delay circuit, thereby not depending on wave forms of the external clock and also the gates connected between the respective single-phase pulse generating circuits are switching-controlled to enable the frequency of the output clock to be variable.

    摘要翻译： 串联连接多个单相脉冲发生器电路的时钟发生器，包括RS触发器和延迟电路，用于通过控制RS翻转的另一个输出的门限定RS触发器上的一个输出的脉冲宽度 使得最终时钟频率可通过切换每个门的控制而变化，由此每个单相时钟的脉冲宽度由延迟电路的延迟持续时间定义，从而不依赖于外部时钟的波形， 连接在各个单相脉冲发生电路之间的门也是开关控制的，以使输出时钟的频率可变。

    Layout designing method for a semiconductor integrated circuit device
    2.
    发明授权
    Layout designing method for a semiconductor integrated circuit device 失效
    半导体集成电路器件的布局设计方法

    公开(公告)号：US5365454A

    公开(公告)日：1994-11-15

    申请号：US777704

    申请日：1991-10-17

    申请人： Shinichi Nakagawa ,  Hiroyuki Kawai

    发明人： Shinichi Nakagawa ,  Hiroyuki Kawai

    IPC分类号： H01L21/82 ,  G06F17/50 ,  H01L27/118 ,  G06F15/60

    CPC分类号： G06F17/5068 ,  H01L27/11807

    摘要： In a layout designing method for an LSI by a CMOS standard cell method, layout cells (standard layout patterns) which respectively correspond to logical function units are selected from a library. In this selection, the respective layout cells are selected from the library as patterns which are divided into p-type layout cells and n-type layout cells. The p-type layout cells and the n-type layout cells are arranged in accordance with a predetermined logical circuit diagram. Interconnection patterns for interconnecting the p-type layout cells and for interconnecting the n-type layout cells are arranged in accordance with the logical circuit diagram. An excessive interconnection region can be minimized, and efficient interconnections can be achieved. Therefore, an occupied plane area can be reduced in the layout design.

    摘要翻译： 在通过CMOS标准单元方法的LSI的布局设计方法中，从库中选择分别对应于逻辑功能单元的布局单元（标准布局图案）。 在该选择中，将各个布局单元从库中选择为分为p型布局单元和n型布局单元的图案。 p型布局单元和n型布局单元根据预定的逻辑电路图布置。 用于互连p型布局单元和用于互连n型布局单元的互连模式根据逻辑电路图布置。 可以最小化过度的互连区域，并且可以实现有效的互连。 因此，布局设计中可以减少占用面积。

    Power supply apparatus and power supply method
    3.
    发明授权
    Power supply apparatus and power supply method 有权
    电源装置及电源方式

    公开(公告)号：US08324873B2

    公开(公告)日：2012-12-04

    申请号：US12636764

    申请日：2009-12-13

    申请人： Shinichi Nakagawa ,  Masahiro Natsume ,  Katsuyuki Yasukouchi

    发明人： Shinichi Nakagawa ,  Masahiro Natsume ,  Katsuyuki Yasukouchi

    IPC分类号： G05F1/613

    CPC分类号： H02M3/1584

    摘要： A power supply apparatus is provided which includes: a first switch provided between an inductor and a terminal to which a reference voltage is applied; a second switch provided between the inductor and an output terminal; a first comparator circuit that compares an input voltage with a first comparison voltage; a signal generating circuit that outputs a frequency signal according to an output from the first comparator circuit; and a first control circuit that controls the first and second switches based on an output from the signal generating circuit to control an electrical current flowing into the inductor.

    摘要翻译： 提供了一种电源装置，其包括：设置在电感器和施加了参考电压的端子之间的第一开关; 设置在电感器和输出端子之间的第二开关; 第一比较器电路，其将输入电压与第一比较电压进行比较; 信号发生电路，其根据来自所述第一比较器电路的输出输出频率信号; 以及第一控制电路，其基于来自信号发生电路的输出来控制第一和第二开关，以控制流入电感器的电流。

    Method for manufacturing semiconductor device
    4.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07910431B2

    公开(公告)日：2011-03-22

    申请号：US12149320

    申请日：2008-04-30

    申请人： Koji Takahashi ,  Shinichi Nakagawa

    发明人： Koji Takahashi ,  Shinichi Nakagawa

    IPC分类号： H01L21/336

    CPC分类号： H01L27/0207 ,  G11C16/0466 ,  H01L27/0266 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11546

    摘要： On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural contact plugs connected respectively to a control gate of the nonvolatile memory cell, a source or a drain of the nMOS transistor, and a source or a drain of the pMOS transistor. Thereafter, there is formed a single-layer wiring connecting the control gate to the sources or drains of the nMOS transistor and the pMOS transistor via the plural contact plugs.

    摘要翻译： 在Si衬底的表面上形成非易失性存储单元，nMOS晶体管和pMOS晶体管，然后形成覆盖非易失性存储单元，nMOS晶体管和pMOS晶体管的层间绝缘膜。 接下来，在层间绝缘膜中，形成有分别连接到非易失性存储单元的控制栅极，nMOS晶体管的源极或漏极以及pMOS晶体管的源极或漏极的多个接触插塞。 此后，形成了通过多个接触插塞将控制栅极连接到nMOS晶体管和pMOS晶体管的源极或漏极的单层布线。

    WDM optical transmission system and an optical transmission line thereof
    5.
    发明授权
    WDM optical transmission system and an optical transmission line thereof 失效
    WDM光传输系统及其光传输线

    公开(公告)号：US06744990B1

    公开(公告)日：2004-06-01

    申请号：US09434679

    申请日：1999-11-05

    申请人： Masatoshi Suzuki ,  Noriyuki Takeda ,  Noboru Edagawa ,  Hideaki Tanaka ,  Shinichi Nakagawa ,  Hidenori Taga ,  Koji Goto

    发明人： Masatoshi Suzuki ,  Noriyuki Takeda ,  Noboru Edagawa ,  Hideaki Tanaka ,  Shinichi Nakagawa ,  Hidenori Taga ,  Koji Goto

    IPC分类号： H04B1012

    CPC分类号： H04B10/2935 ,  H04B10/25253 ,  H04J14/0221

    摘要： An object of the present invention is to realize almost the same transmission characteristic in all wavelengths at a transmission rate of 10 Gb/s or more. An optical transmitter 10 outputs WDM signal light multiplexed with signal light of a plurality of wavelengths toward an optical transmission line 12. The optical transmission line 12 comprises an optical transmission fiber 14, an optical repeating amplifier 16 and a dispersion compensating fiber 18. The gain characteristic of the optical repeating amplifier 16 is set so that the gain becomes the maximum at the effective zero dispersion wavelength of the optical transmission line 12 and that lowers inversely proportional to the distance from the effective zero dispersion wavelength. The whole optical transmission line 12 is set so that the peak power deviation between the effective zero dispersion wavelength &lgr;0 and the wavelength &lgr;1 or &lgr;n on both end becomes approximately 4 dB.

    摘要翻译： 本发明的目的是以10Gb / s以上的传输速率实现所有波长的几乎相同的传输特性。 光发送器10将与多个波长的信号光复用的WDM信号光输出到光传输线12.光传输线12包括光传输光纤14，光中继放大器16和色散补偿光纤18.增益 光学重复放大器16的特性被设置为使得增益在光传输线路12的有效零色散波长处变为最大值，并且降低与距有效零色散波长的距离成反比。 整个光传输线路12被设置为使得有效零色散波长λ0和两端的波长λ1或兰博丹之间的峰值功率偏差变为大约4dB。

    Semiconductor device with delay correction function
    6.
    发明授权
    Semiconductor device with delay correction function 失效
    具有延迟校正功能的半导体器件

    公开(公告)号：US06720811B2

    公开(公告)日：2004-04-13

    申请号：US10193251

    申请日：2002-07-12

    申请人： Minobu Yazawa ,  Shinichi Nakagawa ,  Yasushi Wada

    发明人： Minobu Yazawa ,  Shinichi Nakagawa ,  Yasushi Wada

    IPC分类号： H03L700

    CPC分类号： H03K5/135 ,  G06F1/10 ,  H03K5/133 ,  H03K2005/00078

    摘要： A semiconductor device includes a delay amount measuring unit, multiple delay sections and a correction signal generating unit. The delay amount measuring unit for measures an actual delay amount corresponding to a specified delay amount by supplying a clock signal with a known period to multiple 1-ns-delay strings with a preassigned delay amount, and by detecting phase variations of the clock signal by the 1-ns-delay strings. The delay sections includes a delay string capable of freely adjusting a connection number of its delay elements. The correction signal generating unit generates a correction signal for enabling each of the delay sections to correct the connection number of the delay strings such that each delay section has a desired delay amount, in accordance with the actual delay amount corresponding to the specified delay amount and measured by the delay measuring unit.

    摘要翻译： 半导体器件包括延迟量测量单元，多个延迟部分和校正信号生成单元。 延迟量测量单元，用于通过向具有预分配的延迟量的多个1-ns延迟串提供具有已知周期的时钟信号，并且通过检测时钟信号的相位变化来检测相应于指定延迟量的实际延迟量， 1 ns延迟字符串。 延迟部分包括能够自由地调节其延迟元件的连接数量的延迟串。 校正信号生成单元根据与规定的延迟量对应的实际延迟量，生成用于使每个延迟部分能够校正延迟串的连接数，使得每个延迟部分具有期望的延迟量的校正信号，以及 由延迟测量单元测量。

    Non-volatile semiconductor memory device having a floating gate with protruding conductive side-wall portions
    10.
    发明授权
    Non-volatile semiconductor memory device having a floating gate with protruding conductive side-wall portions 有权
    具有具有突出的导电侧壁部分的浮动栅极的非易失性半导体存储器件

    公开(公告)号：US06172394B2

    公开(公告)日：2001-01-09

    申请号：US09302398

    申请日：1999-04-30

    申请人： Shinichi Nakagawa

    发明人： Shinichi Nakagawa

    IPC分类号： H01L29788

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

    摘要： A non-volatile semiconductor memory device includes memory cells each having a duplicate gate structure in which a floating gate and a control gate are stacked. Each memory cell includes a semiconductor substrate of a first conductivity type; a first gate insulation film formed on the semiconductor substrate; a first conductive film formed on the first gate insulation film and constituting a portion of the floating gate; first and second semiconductor regions of a second conductivity type opposite to the first conductivity type, formed on the semiconductor substrate so as to be self-aligned with side walls of the first conductive film; conductive side-wall portions formed additionally formed on the side walls so as to protrude from a top surface of the first conductive film and to overlap the first and second semiconductor regions, and constituting the remaining portion of the floating gate; a second gate insulation film formed to cover the first conductive film and the conductive side-wall portions; and a second conductive film formed on the second gate insulation film and constituting the control gate. This structure can improve the write efficiency and the erasure efficiency, and reduce the cell area and voltages to be applied to each cell in the write operation and the erasure operation.

    摘要翻译： 非挥发性半导体存储器件包括存储单元，每个存储单元具有重叠的栅极结构，其中堆叠浮置栅极和控制栅极。 每个存储单元包括第一导电类型的半导体衬底; 形成在所述半导体基板上的第一栅极绝缘膜; 形成在第一栅绝缘膜上并构成浮栅的一部分的第一导电膜; 形成在半导体衬底上以与第一导电膜的侧壁自对准的与第一导电类型相反的第二导电类型的第一和第二半导体区域; 导电侧壁部分另外形成在侧壁上以从第一导电膜的顶表面突出并且与第一和第二半导体区域重叠，并且构成浮动栅极的剩余部分; 形成为覆盖所述第一导电膜和所述导电侧壁部的第二栅极绝缘膜; 以及形成在第二栅极绝缘膜上并构成控制栅极的第二导电膜。 该结构可以提高写入效率和擦除效率，并且在写入操作和擦除操作中减小要施加到每个单元的单元面积和电压。