公开(公告)号：US07649221B2

公开(公告)日：2010-01-19

申请号：US11951026

申请日：2007-12-05

申请人： Makoto Sakuma ,  Atsuhiro Sato

发明人： Makoto Sakuma ,  Atsuhiro Sato

IPC分类号： H01L29/72

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.

摘要翻译： 非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准 沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及 电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

公开(公告)号：US07505312B2

公开(公告)日：2009-03-17

申请号：US11447963

申请日：2006-06-07

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

IPC分类号： G11C16/10

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.

摘要翻译： 公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体 存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。 在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。 在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

公开(公告)号：US07494869B2

公开(公告)日：2009-02-24

申请号：US11338707

申请日：2006-01-25

申请人： Atsuhiro Sato

发明人： Atsuhiro Sato

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  G11C11/5621 ,  G11C16/0483 ,  H01L21/76232 ,  H01L27/11521 ,  H01L27/11524

摘要： A manufacturing method of a semiconductor integrated circuit device is disclosed. A gate insulating film is formed on a semiconductor substrate. A first film used as floating gates is formed on the gate insulating film. Trenches are formed in the substrate through the first film. Insulating materials are embedded in the trenches. The insulating materials are set back at least in a plane direction. Second films used as floating gates are formed between the side walls of the insulating materials without making directly contact with the side walls of the insulating materials. The insulating materials are set back from spaces caused between the insulating materials and the second films.

摘要翻译： 公开了一种半导体集成电路器件的制造方法。 在半导体衬底上形成栅极绝缘膜。 在栅极绝缘膜上形成用作浮栅的第一膜。 通过第一膜在基板中形成沟槽。 绝缘材料嵌入沟槽中。 绝缘材料至少在平面方向回缩。 在绝缘材料的侧壁之间形成用作浮栅的第二膜，而不与绝缘材料的侧壁直接接触。 绝缘材料从绝缘材料和第二薄膜之间的空间回放。

公开(公告)号：US20060258092A1

公开(公告)日：2006-11-16

申请号：US11338707

申请日：2006-01-25

申请人： Atsuhiro Sato

发明人： Atsuhiro Sato

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/28273 ,  G11C11/5621 ,  G11C16/0483 ,  H01L21/76232 ,  H01L27/11521 ,  H01L27/11524

摘要： A manufacturing method of a semiconductor integrated circuit device is disclosed. A gate insulating film is formed on a semiconductor substrate. A first film used as floating gates is formed on the gate insulating film. Trenches are formed in the substrate through the first film. Insulating materials are embedded in the trenches. The insulating materials are set back at least in a plane direction. Second films used as floating gates are formed between the side walls of the insulating materials without making directly contact with the side walls of the insulating materials. The insulating materials are set back from spaces caused between the insulating materials and the second films.

公开(公告)号：US07122430B2

公开(公告)日：2006-10-17

申请号：US11311262

申请日：2005-12-20

申请人： Atsuhiro Sato ,  Makoto Sakuma ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Makoto Sakuma ,  Fumitaka Arai

IPC分类号： H01I21/336 ,  H01I21/8238

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529

摘要： The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.

公开(公告)号：US20050067652A1

公开(公告)日：2005-03-31

申请号：US10868806

申请日：2004-06-17

申请人： Makoto Sakuma ,  Atsuhiro Sato

发明人： Makoto Sakuma ,  Atsuhiro Sato

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115

摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.

摘要翻译： 非易失性半导体存储器包括分别具有浮置栅极，控制栅极和栅极间绝缘膜的多个存储单元晶体管，其分别布置在相应的浮置栅极和相应的控制栅极之间，并沿着列方向展开; 以及沿着行方向以恒定间距部署的器件隔离区域，沿着列方向形成条纹图案。 控制栅极沿着行方向连续展开，并且栅极间绝缘膜沿列方向串联并沿行方向以恒定的间距彼此分离。

公开(公告)号：US20050003619A1

公开(公告)日：2005-01-06

申请号：US10717719

申请日：2003-11-21

申请人： Masayuki Tanaka ,  Atsuhiro Sato ,  Hiroki Yamashita ,  Ichiro Mizushima ,  Yoshio Ozawa

发明人： Masayuki Tanaka ,  Atsuhiro Sato ,  Hiroki Yamashita ,  Ichiro Mizushima ,  Yoshio Ozawa

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.

摘要翻译： 半导体存储器包括存储单元矩阵，其包括沿列方向延伸的器件隔离膜，交替地布置在单元列之间; 第一导电层的顶表面低于器件隔离膜; 布置在相应的第一导电层上的电极间电介质，所述电极间电介质的介电常数大于氧化硅的介电常数; 和沿着行方向延伸的第二导电层，每个第二导电层布置在电极间电介质和器件隔离膜上，使得第二导电层可以被沿着行方向归属布置的存储单元晶体管共享 到不同的细胞柱。

公开(公告)号：US08159880B2

公开(公告)日：2012-04-17

申请号：US13164486

申请日：2011-06-20

申请人： Atsuhiro Sato ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Fumitaka Arai

IPC分类号： G11C16/00

CPC分类号： G11C11/5628 ,  G11C16/0483

摘要： In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor.

摘要翻译： 在第一和第二选择栅极晶体管被截止并且第一电压被施加到第二存储单元晶体管的控制栅极的状态下，第二存储单元晶体管连接到从存储器中选择的第一存储单元晶体管的源极线侧 单元晶体管并且要被切断，高于第一电压的第二电压并且使得在存储单元晶体管导通时保持未选择的多个第三存储单元晶体管被施加到第三存储单元晶体管的控制栅极 之后，通过向第一存储单元的控制栅极施加高于第二电压的第三电压，将第一存储单元晶体管的阈值电压改变为高于与擦除状态相对应的第一阈值电压的阈值电压 晶体管。

公开(公告)号：US08139407B2

公开(公告)日：2012-03-20

申请号：US12955621

申请日：2010-11-29

申请人： Atsuhiro Sato ,  Keiji Shuto ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Keiji Shuto ,  Fumitaka Arai

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5642

摘要： A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.

摘要翻译： 非易失性半导体存储器件设置有存储单元阵列，判断电位校正电路和读出电路。 在存储单元阵列中，以矩阵形式布置多个存储单元，并且阵列包括作为读出对象的第一存储单元和与第一存储单元相邻设置的第二存储单元。 判定电位校正电路根据第二存储单元的阈值校正判定电位。 读出电路通过使用校正的判断电位读出作为读出对象的第一存储单元。

公开(公告)号：US08133782B2

公开(公告)日：2012-03-13

申请号：US13028730

申请日：2011-02-16

申请人： Hiroshi Akahori ,  Wakako Takeuchi ,  Atsuhiro Sato

发明人： Hiroshi Akahori ,  Wakako Takeuchi ,  Atsuhiro Sato

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42336

摘要： A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.

摘要翻译： 存储器件包括：半导体衬底，以行和列形成在衬底上方的存储元件，位线和字线与各个列和行中的存储元件选择性地连接，每个存储元件包括形成在衬底上的第一栅极绝缘体 ，形成在第一栅极绝缘体上的电荷累积层，形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极，其中比率r / d不小于0.5，其中r：a 上角部的曲率半径或电荷蓄积层的表面粗糙度，d：沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。