公开(公告)号：US08728931B2

公开(公告)日：2014-05-20

申请号：US13553977

申请日：2012-07-20

申请人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

发明人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC分类号： H01L21/4763

CPC分类号： H01L23/49866 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

摘要翻译： 形成互连结构的方法包括在基板的电介质层中形成凹部。 形成粘合阻挡层以使凹部成线。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 该凹部填充有填充层。

公开(公告)号：US20130049199A1

公开(公告)日：2013-02-28

申请号：US13222469

申请日：2011-08-31

申请人： Paul R. Besser ,  Roy A. Carruthers ,  Christopher P. D'Emic ,  Christian Lavoie ,  Conal E. Murray ,  Kazuya Ohuchi ,  Christopher Scerbo ,  Bin Yang

发明人： Paul R. Besser ,  Roy A. Carruthers ,  Christopher P. D'Emic ,  Christian Lavoie ,  Conal E. Murray ,  Kazuya Ohuchi ,  Christopher Scerbo ,  Bin Yang

IPC分类号： H01L23/532 ,  H01L21/336 ,  H01L21/768

CPC分类号： H01L21/26506 ,  H01L21/28518 ,  H01L29/00 ,  H01L29/665 ,  H01L29/7833

摘要： Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to form an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A suicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.

摘要翻译： 具有改进的稀土硅化物形态的硅化技术用于制造半导体器件触点。 例如，用于形成硅化物的方法包括用非晶化物质注入硅层以在硅层中形成非晶硅区域，并在与非晶硅区域接触的硅层上沉积稀土金属膜。 然后进行自杀处理以组合稀土金属膜和非晶硅区域，以在硅层上形成硅化物膜。

公开(公告)号：US07994038B2

公开(公告)日：2011-08-09

申请号：US12366378

申请日：2009-02-05

申请人： Karthik Ramani ,  Paul R. Besser

发明人： Karthik Ramani ,  Paul R. Besser

IPC分类号： H01L21/3205

CPC分类号： H01L21/823807 ,  H01L21/28052 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/458 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

摘要： Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.

摘要翻译： 晶体管器件形成有硅化镍层，配制成防止去除上覆应力衬垫时的退化。 实施方案包括具有镍化硅层的晶体管，其铂组分梯度朝向其上表面增加铂含量，即铂在远离栅电极和源/漏区的方向上增加。 实施例包括形成具有第一量的铂的第一镍层，并在第一层镍上形成具有第二量铂的第二层镍，第二重量百分比的铂大于第一重量百分数。 然后将镍层退火以形成铂化合物梯度朝向上表面逐渐增加的铂硅化镍层。 铂浓度梯度在后续处理期间保护硅化镍层，如在蚀刻期间去除上覆的应力衬垫，从而避免器件性能的降低。

公开(公告)号：US07910996B2

公开(公告)日：2011-03-22

申请号：US12496133

申请日：2009-07-01

申请人： Paul R. Besser ,  Scott D. Luning

发明人： Paul R. Besser ,  Scott D. Luning

IPC分类号： H01L29/12

CPC分类号： H01L29/66628 ,  H01L29/66772

摘要： A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

摘要翻译： 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

公开(公告)号：US20080182407A1

公开(公告)日：2008-07-31

申请号：US11669700

申请日：2007-01-31

申请人： Jun Zhai ,  Christy Woo ,  Kok-Yong Yiang ,  Paul R. Besser ,  Richard C. Blish ,  Christine Hau-Reige

发明人： Jun Zhai ,  Christy Woo ,  Kok-Yong Yiang ,  Paul R. Besser ,  Richard C. Blish ,  Christine Hau-Reige

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76852 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A via is formed in contact with a conductive line, whereby the via is offset from the conductive line so that the via extends beyond the conductive line. In accordance with a specific embodiment, a portion of the via contacts a sidewall of the conductive line.

摘要翻译： 通孔形成为与导电线接触，由此通孔偏离导线，使得通孔延伸超过导线。 根据具体实施例，通孔的一部分接触导线的侧壁。

公开(公告)号：US07049666B1

公开(公告)日：2006-05-23

申请号：US10859286

申请日：2004-06-01

申请人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

发明人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L29/94 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成一个薄的绝缘层。 在薄绝缘层和栅极上形成硅化物。 在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。

公开(公告)号：US06867428B1

公开(公告)日：2005-03-15

申请号：US10282712

申请日：2002-10-29

申请人： Paul R. Besser ,  Eric N. Paton ,  Qi Xiang

发明人： Paul R. Besser ,  Eric N. Paton ,  Qi Xiang

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/6659 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

摘要： An n-type strained silicon MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon regions are provided in the silicon geranium layer at opposing sides of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon regions. By forming the shallow source and drain extensions in silicon regions rather than in silicon germanium, source and drain extension distortions caused by the enhanced diffusion rate of arsenic in silicon germanium are avoided.

摘要翻译： n型应变硅MOSFET利用形成在硅锗衬底上的应变硅沟道区。 在应变硅沟道区的相对侧的硅天竺塔层中设置有硅区，并且在硅区域中注入浅的源极和漏极延伸。 通过在硅区域而不是在硅锗中形成浅的源极和漏极延伸部分，避免了由锗在锗中增加的扩散速率引起的源极和漏极扩展失真。

公开(公告)号：US06661067B1

公开(公告)日：2003-12-09

申请号：US10260514

申请日：2002-10-01

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

IPC分类号： H01L2994

CPC分类号： H01L29/665 ,  H01L21/3115 ,  Y10S257/90

摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

摘要翻译： 通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面来形成具有减少的游离硅的表面区域，防止栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

公开(公告)号：US06611576B1

公开(公告)日：2003-08-26

申请号：US09780476

申请日：2001-02-12

申请人： Paul R. Besser ,  Paul L. King

发明人： Paul R. Besser ,  Paul L. King

IPC分类号： G01N23223

CPC分类号： C23C14/545 ,  G01N23/223 ,  G01N2223/076

摘要： A novel method of automatically controlling thickness of a metal film during film deposition in a deposition chamber. The method involves producing an X-ray beam directed to the metal film deposited on a wafer in a deposition chamber, and detecting X-ray fluorescence of the metal film. The thickness of the metal film determined based on the detected X-ray fluorescence is compared with a preset value to continue deposition if the determined thickness is less than the preset value. Deposition is stopped when the determined thickness reaches the preset value.

摘要翻译： 一种在淀积室中成膜期间自动控制金属膜厚度的新方法。 该方法包括产生指向沉积在沉积室中的晶片上的金属膜的X射线束，并且检测金属膜的X射线荧光。 如果确定的厚度小于预设值，则将基于检测到的X射线荧光确定的金属膜的厚度与预设值进行比较以继续沉积。 当确定的厚度达到预设值时，停止沉积。

公开(公告)号：US06602754B1

公开(公告)日：2003-08-05

申请号：US10059039

申请日：2002-01-30

申请人： George J. Kluth ,  Minh Van Ngo ,  Paul R. Besser

发明人： George J. Kluth ,  Minh Van Ngo ,  Paul R. Besser

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/265

摘要： Bridging between silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by implanting the exposed surfaces of the silicon nitride sidewall spacers with nitrogen to create a surface region having an increased nitrogen concentration. Embodiments include implanting the silicon nitride sidewall spacers with nitrogen such that the nitrogen concentration of the exposed surface is increased by about 5% to about 15%, thereby substantially preventing the formation of metal silicide on the sidewall spacers.

摘要翻译： 通过用氮气注入氮化硅侧壁间隔物的暴露表面以产生具有增加的氮浓度的表面区域来防止在栅电极上的硅化物层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氮气注入氮化硅侧壁间隔物，使得暴露表面的氮浓度增加约5％至约15％，从而基本上防止在侧壁间隔物上形成金属硅化物。