公开(公告)号：US20230268376A1

公开(公告)日：2023-08-24

申请号：US17827648

申请日：2022-05-27

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L28/60 ,  H01L23/5226 ,  H01L23/5223 ,  H01L21/76877 ,  H01L21/76843 ,  H01L21/7687

Abstract: A metal-insulator-metal (MIM) capacitor module includes an outer electrode, an insulator, an inner electrode, an outer electrode extension structure, an inner electrode contact element, and an outer electrode contact element. The outer electrode includes a plurality of vertically-extending outer electrode sidewalls. The insulator is formed in an opening defined by the vertically-extending outer electrode sidewalls, and includes a plurality of vertically-extending insulator sidewalls. The inner electrode formed in an interior opening defined by the insulator. The outer electrode extension structure extends laterally from a particular vertically-extending outer electrode sidewall. The inner electrode contact element and outer electrode contact element are formed in a metal layer. The inner electrode contact element is electrically connected to the inner electrode, and the outer electrode contact element is electrically connected to the outer electrode extension structure.

公开(公告)号：US20230260938A1

公开(公告)日：2023-08-17

申请号：US18141621

申请日：2023-05-01

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bony Chen ,  Yaojian Leng ,  Gerald Marsico ,  Julius Kovats

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L24/89 ,  H01L2224/0361 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05639 ,  H01L2224/05724 ,  H01L2224/05839 ,  H01L2224/08225 ,  H01L2224/80895

Abstract: An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

公开(公告)号：US11723222B2

公开(公告)日：2023-08-08

申请号：US17074848

申请日：2020-10-20

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato ,  Bomy Chen

IPC: H10K19/00 ,  H10K19/10 ,  H01L49/02

CPC classification number: H10K19/201 ,  H10K19/10 ,  H01L28/10

Abstract: An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.

公开(公告)号：US11715757B2

公开(公告)日：2023-08-01

申请号：US18074617

申请日：2022-12-05

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L23/52 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L23/5223

Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.

公开(公告)号：US20230160836A1

公开(公告)日：2023-05-25

申请号：US18093032

申请日：2023-01-04

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: G01N21/95 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L31/103 ,  H01L21/66 ,  G01N21/47 ,  G01N21/88 ,  H01L31/02 ,  G01N17/02

CPC classification number: G01N21/9501 ,  H01L23/53238 ,  H01L23/528 ,  H01L23/5226 ,  H01L31/103 ,  H01L22/14 ,  G01N21/47 ,  G01N21/8851 ,  H01L31/02005 ,  G01N17/02 ,  G01N2201/06113 ,  G01N2021/4735

Abstract: Systems and methods for monitoring copper corrosion in an integrated circuit (IC) device are disclosed. A corrosion-sensitive structure formed in the IC device may include a p-type active region adjacent an n-type active region to define a p-n junction space charge region. A copper region formed over the silicon may be connected to both the p-region and n-region by respective contacts, to thereby define a short circuit. Light incident on the p-n junction space charge region, e.g., during a CMP process, creates a current flow through the metal region via the short circuit, which drives chemical reactions that cause corrosion in the copper region. Due to the short circuit configuration, the copper region is highly sensitive to corrosion. The corrosion-sensitive structure may be arranged with less corrosion-sensitive copper structures in the IC device, with the corrosion-sensitive structure used as a proxy to monitor for copper corrosion in the IC device.

公开(公告)号：US20230099856A1

公开(公告)日：2023-03-30

申请号：US17665749

申请日：2022-02-07

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Yaojian Leng ,  Julius Kovats

IPC: H01L23/498 ,  H01L23/50 ,  H01L25/065

Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

公开(公告)号：US20230081749A1

公开(公告)日：2023-03-16

申请号：US17536597

申请日：2021-11-29

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L27/01 ,  H01L23/522 ,  H01L21/768

Abstract: An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.

公开(公告)号：US11600566B2

公开(公告)日：2023-03-07

申请号：US17233311

申请日：2021-04-16

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/525 ,  H01L21/768

Abstract: An electronic fuse (e-fuse) module may be formed in an integrated circuit device. The e-fuse module may include a pair of metal e-fuse terminals (e.g., copper terminals) and an e-fuse element formed directly on the metal e-fuse terminals to define a conductive path between the pair of metal e-fuse terminals through the e-fuse element. The metal e-fuse terminals may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The e-fuse element may be formed by depositing and patterning a diffusion barrier layer over the metal e-fuse terminals and interconnect elements formed in the metal interconnect layer. The e-fuse element may be formed from a material that provides a barrier against metal diffusion (e.g., copper diffusion) from each of the metal e-fuse terminals and interconnect elements. For example, the e-fuse element may be formed from titanium tungsten (TiW) or titanium tungsten nitride (TiW2N).

公开(公告)号：US11573189B2

公开(公告)日：2023-02-07

申请号：US16683987

申请日：2019-11-14

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: G01N21/95 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L31/103 ,  H01L21/66 ,  G01N21/47 ,  G01N21/88 ,  H01L31/02 ,  G01N17/02

Abstract: Systems and methods for monitoring copper corrosion in an integrated circuit (IC) device are disclosed. A corrosion-sensitive structure formed in the IC device may include a p-type active region adjacent an n-type active region to define a p-n junction space charge region. A copper region formed over the silicon may be connected to both the p-region and n-region by respective contacts, to thereby define a short circuit. Light incident on the p-n junction space charge region, e.g., during a CMP process, creates a current flow through the metal region via the short circuit, which drives chemical reactions that cause corrosion in the copper region. Due to the short circuit configuration, the copper region is highly sensitive to corrosion. The corrosion-sensitive structure may be arranged with less corrosion-sensitive copper structures in the IC device, with the corrosion-sensitive structure used as a proxy to monitor for copper corrosion in the IC device.

公开(公告)号：US11545544B2

公开(公告)日：2023-01-03

申请号：US17155431

申请日：2021-01-22

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L49/02

Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.