公开(公告)号：US20230289270A1

公开(公告)日：2023-09-14

申请号：US18121312

申请日：2023-03-14

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Daniele Balluchi ,  Niccolò Izzo ,  Alessandro Orlando

IPC: G06F11/263 ,  G06F11/273 ,  G06F11/22

CPC classification number: G06F11/263 ,  G06F11/273 ,  G06F11/2221

Abstract: An electronic device can be configured to enable a host to indirectly control testing associated with the electronic device. The interface between the host and the electronic device can be abstract, such that the host does not have direct control over the electronic device. Examples of the electronic device include a memory device and a power management integrated circuit. The electronic device can allow the host to discover a quantity of tests supported by the electronic device and corresponding test descriptors. The electronic device can interact with the host to configure tests and/or reporting of test results.

公开(公告)号：US11579970B2

公开(公告)日：2023-02-14

申请号：US17375832

申请日：2021-07-14

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Daniele Balluchi

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

Abstract: Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.

公开(公告)号：US11494122B2

公开(公告)日：2022-11-08

申请号：US17140625

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

公开(公告)号：US20220261363A1

公开(公告)日：2022-08-18

申请号：US17673731

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Daniele Balluchi ,  Paolo Amato ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F13/16

Abstract: Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The central controller portion is configured to cause performance of a memory operation and comprises a cache memory to buffer data associated performance of the memory operation, a security component configured to encrypt the data before storing the data in the first type of memory device or the second type of memory device, and error correction code (ECC) circuitry to ECC encode and ECC decode the data.

公开(公告)号：US11379139B2

公开(公告)日：2022-07-05

申请号：US17020460

申请日：2020-09-14

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38 ,  G06F9/50 ,  G11C14/00 ,  G11C13/00

Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

公开(公告)号：US11151027B2

公开(公告)日：2021-10-19

申请号：US16553024

申请日：2019-08-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G06F3/06

Abstract: Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. The host is configured to provide a plurality of memory access requests to the memory, to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, and to request execution of the memory access request responsive to the ready status information.

公开(公告)号：US20210319829A1

公开(公告)日：2021-10-14

申请号：US16846481

申请日：2020-04-13

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Paolo Amato ,  Graziano Mirichigni ,  Danilo Caraccio ,  Marco Sforzin ,  Marco Dallabora

IPC: G11C13/00

Abstract: An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.

公开(公告)号：US10956290B2

公开(公告)日：2021-03-23

申请号：US16214701

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US20210064261A1

公开(公告)日：2021-03-04

申请号：US17020460

申请日：2020-09-14

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38 ,  G06F9/50 ,  G11C14/00

Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

公开(公告)号：US10809942B2

公开(公告)日：2020-10-20

申请号：US15927383

申请日：2018-03-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06 ,  G06F12/10

Abstract: An example apparatus comprises a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to cause data associated with a virtual memory location of the host to be selectively transferred to the hybrid memory system responsive to a determination that a main memory of the host experiences threshold amount of resource utilization.