公开(公告)号：US10140222B1

公开(公告)日：2018-11-27

申请号：US15642906

申请日：2017-07-06

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Peter R. Castro

IPC: G06F13/16 ,  G06F13/42 ,  G06F3/02 ,  G06F12/02 ,  G11C7/10 ,  G06F3/06 ,  G06F13/40

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

公开(公告)号：US11467654B2

公开(公告)日：2022-10-11

申请号：US17327282

申请日：2021-05-21

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G06F1/3296 ,  G06F13/20 ,  G06F13/40 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3221

Abstract: A power management integrated circuit (PMIC) is described for providing system management bus (SMB) isolation, along with memory sub-systems which include such a PMIC and methods of operating such devices. In one embodiment, a PMIC comprises a voltage supply input, power management circuitry, and elements of a SMB. The SMB elements can include an SMB input, an SMB hot swap controller coupled to the SMB input, one or more SMBs, and one or more SMB outputs. When integrated with a memory sub-system, one SMB output can be connected to a memory controller and another SMB output to a microcontroller. During different power states (e.g., normal or low power states), certain outputs can be isolated in order to manage communications on the SMB during the different power states of the memory sub-system using the PMIC.

公开(公告)号：US11436167B2

公开(公告)日：2022-09-06

申请号：US17175002

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Peter R. Castro

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/42 ,  G06F13/40 ,  G11C7/10 ,  G06F12/02

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

公开(公告)号：US20220113786A1

公开(公告)日：2022-04-14

申请号：US17560790

申请日：2021-12-23

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G06F1/3234 ,  G11C16/30 ,  G06F1/26

Abstract: An apparatus includes a power management integrated circuit (PMIC) and a power translator component coupled to the PMIC. The power translator component supplies power to the PMIC. The power translator component can further receive, from the PMIC, an indication that the PMIC has experienced a thermal event and responsive to receipt of the indication that the PMIC has experienced the thermal event, prevent powering of the PMIC.

公开(公告)号：US11073897B2

公开(公告)日：2021-07-27

申请号：US16524852

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G06F1/3296 ,  G06F13/20 ,  G06F13/40 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3221

Abstract: A power management integrated circuit (PMIC) is described for providing system management bus (SMB) isolation, along with memory sub-systems which include such a PMIC and methods of operating such devices. In one embodiment, a PMIC comprises a voltage supply input, power management circuitry, and elements of a SMB. The SMB elements can include an SMB input, an SMB hot swap controller coupled to the SMB input, one or more SMBs, and one or more SMB outputs. When integrated with a memory sub-system, one SMB output can be connected to a memory controller and another SMB output to a microcontroller. During different power states (e.g., normal or low power states), certain outputs can be isolated in order to manage communications on the SMB during the different power states of the memory sub-system using the PMIC.

公开(公告)号：US11073855B2

公开(公告)日：2021-07-27

申请号：US16525393

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: H02M3/18 ,  G05F1/575 ,  H02M3/158 ,  H02M1/00

Abstract: Various embodiments described herein provide a system that uses a capacitor-based power converter to generate a gate voltage (e.g., boot strap voltage) for a buck converter. According to various embodiments described herein, the capacitor-based power converter includes at least one of a combination of a capacitive voltage divider circuit with a low-dropout (LDO) regulator, or a combination of a capacitive doubler circuit with an LDO regulator, to generate the gate voltage for the buck converter.

公开(公告)号：US20210165751A1

公开(公告)日：2021-06-03

申请号：US17175002

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Peter R. Castro

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/42 ,  G06F13/40 ,  G11C7/10 ,  G06F12/02

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

公开(公告)号：US20210034140A1

公开(公告)日：2021-02-04

申请号：US16524852

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G06F1/3296 ,  G06F13/20

Abstract: A power management integrated circuit (PMIC) is described for providing system management bus (SMB) isolation, along with memory sub-systems which include such a PMIC and methods of operating such devices. In one embodiment, a PMIC comprises a voltage supply input, power management circuitry, and elements of a SMB. The SMB elements can include an SMB input, an SMB hot swap controller coupled to the SMB input, one or more SMBs, and one or more SMB outputs. When integrated with a memory sub-system, one SMB output can be connected to a memory controller and another SMB output to a microcontroller. During different power states (e.g., normal or low power states), certain outputs can be isolated in order to manage communications on the SMB during the different power states of the memory sub-system using the PMIC.

公开(公告)号：US10803909B2

公开(公告)日：2020-10-13

申请号：US16112442

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G06F1/32 ,  G11C5/14 ,  G06F1/3296 ,  G06F1/28 ,  G06F1/3203

Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to output respective operating voltages for the memory sub-system. The power management component comprises a power management integrated circuit (PMIC) and is configured to monitor voltage levels of the plurality of regulators and prevent an event of the memory sub-system from occurring until the monitored voltage levels of a set of the plurality of regulators are determined to have reached respective threshold voltage levels.

公开(公告)号：US10761588B2

公开(公告)日：2020-09-01

申请号：US16059387

申请日：2018-08-09

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Adam J. Hieb

IPC: G06F1/00 ,  G06F1/3234 ,  G06F9/445 ,  G06F1/3296

Abstract: A power management system includes a memory component storing a plurality of configuration profiles. A plurality of configuration pins are operatively coupled to the memory component. One or more of the plurality of configuration pins receive one or more signals to selectively activate one of the plurality of configuration profiles.