公开(公告)号：US20230207019A1

公开(公告)日：2023-06-29

申请号：US18081114

申请日：2022-12-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Lawrence Celso Miranda ,  Sheyang Ning ,  Jeffrey S. McNeil ,  Tomoko Ogura Iwasaki

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/24

Abstract: Control logic in a memory device causes a boost voltage to be applied one or more times to a plurality of unselected wordlines of a block of the memory array, the block comprising a plurality of sub-blocks, and the boost voltage to boost a channel potential of each of the plurality of sub-blocks by an amount each time the boost voltage is applied. The control logic further selectively discharges the amount of boost voltage from one or more of the plurality of sub-blocks after each time the boost voltage is applied according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. Additionally, the control logic causes a single programming pulse to be applied to one or more selected wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

公开(公告)号：US11462281B1

公开(公告)日：2022-10-04

申请号：US17307443

申请日：2021-05-04

Applicant: Micron Technology, Inc.

Inventor： Lawrence Celso Miranda ,  Eric N. Lee ,  Tong Liu ,  Sheyang Ning ,  Cobie B. Loper ,  Ugo Russo

IPC: G11C16/12 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06

Abstract: Control logic in a memory device identifies a first group of wordlines associated with a first subset of memory cells of a set of memory cells to be programmed. A first dynamic start voltage operation including a first set of programming pulses and a first set of program verify operations is executed on a first portion of the first subset of memory cells to identify a first dynamic start voltage level, the executing of the first dynamic start voltage operation includes causing the first set of programming pulses to be applied to at least a portion of the first group of wordlines. A second set of programming pulses including at least one programming pulse having the first dynamic start voltage level are caused to be applied to the first group of wordlines to program a second portion of the first subset of memory cells of the set of memory cells. A second group of wordlines associated with a second subset of memory cells to be programmed is identified. A second dynamic start voltage operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second dynamic start voltage level.

公开(公告)号：US20220187995A1

公开(公告)日：2022-06-16

申请号：US17119576

申请日：2020-12-11

Applicant: Micron Technology, Inc.

Inventor： Sheyang Ning ,  Lawrence Miranda

IPC: G06F3/06 ,  G11C16/08 ,  G11C16/10

Abstract: Control logic in a memory device identifies a request to execute a memory access operation on the memory cell. A first set of pulses corresponding to a first voltage ramp slope level is caused to be applied to the memory cell during a first time interval of the memory access operation. The control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first slope level and the second slope level are different.