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公开(公告)号:US20210056405A1
公开(公告)日:2021-02-25
申请号:US16545837
申请日:2019-08-20
Applicant: Micron Technology, Inc.
Inventor: Samuel E. Bradshaw , Shivasankar Gunasekaran , Sean Stephen Eilert , Ameen D. Akel , Kenneth Marion Curewitz
Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, inputs for the ANN can be obfuscated for centralized training of a master version of the ANN at a first computing device. A second computing device in the system includes memory that stores a local version of the ANN and user data for inputting into the local version. The second computing device includes a processor that extracts features from the user data and obfuscates the extracted features to generate obfuscated user data. The second device includes a transceiver that transmits the obfuscated user data. The first computing device includes a memory that stores the master version of the ANN, a transceiver that receives obfuscated user data transmitted from the second computing device, and a processor that trains the master version based on the received obfuscated user data using machine learning.
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公开(公告)号:US20210056387A1
公开(公告)日:2021-02-25
申请号:US16545813
申请日:2019-08-20
Applicant: Micron Technology, Inc.
Inventor: Sean Stephen Eilert , Shivasankar Gunasekaran , Ameen D. Akel , Kenneth Marion Curewitz , Hongyu Wang
Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, changes to local versions of the ANN can be combined with a master version of the ANN. In the system, a first device can include memory that can store the master version, a second device can include memory that can store a local version of the ANN, and there can be many devices that store local versions of the ANN. The second device (or any other device of the system hosting a local version) can include a processor that can train the local version, and a transceiver that can transmit changes to the local version generated from the training. The first device can include a transceiver that can receive the changes to a local version, and a processing device that can combine the received changes with the master version.
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公开(公告)号:US20200379919A1
公开(公告)日:2020-12-03
申请号:US16424420
申请日:2019-05-28
Applicant: Micron Technology, Inc.
Inventor: Samuel E. Bradshaw , Ameen D. Akel , Kenneth Marion Curewitz , Sean Stephen Eilert , Dmitri Yudanov
IPC: G06F12/1027 , H04L29/08
Abstract: Systems, methods and apparatuses to accelerate accessing of borrowed memory over network connection are described. For example, a memory management unit (MMU) of a computing device can be configured to be connected both to the random access memory over a memory bus and to a computer network via a communication device. The computing device can borrow an amount of memory from a remote device over a network connection using the communication device; and applications running in the computing device can use virtual memory addresses mapped to the borrowed memory. When a virtual address mapped to the borrowed memory is used, the MMU translates the virtual address into a physical address and instruct the communication device to access the borrowed memory.
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公开(公告)号:US12301659B2
公开(公告)日:2025-05-13
申请号:US17899265
申请日:2022-08-30
Applicant: Micron Technology, Inc.
Inventor: Dmitri Yudanov , Ameen D. Akel , Samuel E. Bradshaw , Kenneth Marion Curewitz , Sean Stephen Eilert
IPC: G06F15/16 , G06F12/02 , G06F12/1009 , G06F12/1027 , H04L67/1097 , H04L67/51
Abstract: Systems, methods and apparatuses to provide memory as a service are described. For example, a borrower device is configured to: communicate with a lender device; borrow an amount of memory from the lender device; expand memory capacity of the borrower device for applications running on the borrower device, using at least the local memory of the borrower device and the amount of memory borrowed from the lender device; and service accesses by the applications to memory via communication link between the borrower device and the lender device.
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公开(公告)号:US12248412B2
公开(公告)日:2025-03-11
申请号:US17841448
申请日:2022-06-15
Applicant: Micron Technology, Inc.
Inventor: Kenneth Marion Curewitz , Ameen D. Akel , Hongyu Wang , Sean Stephen Eilert
IPC: G06F13/16 , G06F18/214 , G06N3/08
Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN) as well as different versions of a feature dictionary. In the system, encoded inputs for the ANN can be decoded by the feature dictionary, which allows for encoded input to be sent to a master version of the ANN over a network instead of an original version of the input which usually includes more data than the encoded input. Thus, by using the feature dictionary for training of a master ANN there can be reduction of data transmission.
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公开(公告)号:US11868268B2
公开(公告)日:2024-01-09
申请号:US17665823
申请日:2022-02-07
Applicant: Micron Technology, Inc.
Inventor: Kenneth Marion Curewitz , Sean S. Eilert , Hongyu Wang , Samuel E. Bradshaw , Shivasankar Gunasekaran , Justin M. Eno , Shivam Swami
IPC: G06F12/10 , G06F12/1009 , G06F12/1027
CPC classification number: G06F12/1009 , G06F12/1027 , G06F2212/657 , G06F2212/68
Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).
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公开(公告)号:US11556656B2
公开(公告)日:2023-01-17
申请号:US16582871
申请日:2019-09-25
Applicant: Micron Technology, Inc.
Inventor: Shivam Swami , Sean S. Eilert , Ameen D. Akel , Kenneth Marion Curewitz , Hongyu Wang
Abstract: Methods and apparatus of Exclusive OR (XOR) engine in a random access memory device to accelerate cryptographical operations in processors. For example, an integrated circuit memory device enclosed within a single integrated circuit package can include an XOR engine that is coupled with memory units in the random access memory device (e.g., having dynamic random access memory (DRAM) or non-volatile random access memory (NVRAM)). A processor (e.g., System-on-Chip (SoC) or Central Processing Unit (CPU)) can have encryption logic that performs cryptographical operations using XOR operations that are performed by the XOR engine in the random access memory device using the data in the random access memory device.
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公开(公告)号:US11438414B2
公开(公告)日:2022-09-06
申请号:US16424411
申请日:2019-05-28
Applicant: Micron Technology, Inc.
Inventor: Dmitri Yudanov , Ameen D. Akel , Samuel E. Bradshaw , Kenneth Marion Curewitz , Sean Stephen Eilert
IPC: G06F15/16 , H04L67/1097 , G06F12/1027 , G06F12/1009 , H04L67/51 , G06F12/02
Abstract: Systems, methods and apparatuses to provide memory as a service are described. For example, a borrower device is configured to: communicate with a lender device; borrow an amount of memory from the lender device; expand memory capacity of the borrower device for applications running on the borrower device, using at least the local memory of the borrower device and the amount of memory borrowed from the lender device; and service accesses by the applications to memory via communication link between the borrower device and the lender device.
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公开(公告)号:US11334387B2
公开(公告)日:2022-05-17
申请号:US16424413
申请日:2019-05-28
Applicant: Micron Technology, Inc.
Inventor: Sean Stephen Eilert , Ameen D. Akel , Samuel E. Bradshaw , Kenneth Marion Curewitz , Dmitri Yudanov
IPC: G06F9/50 , G06F12/1009 , G06F12/02 , H04L41/0896 , G06F13/16 , G06F12/08 , G06F12/1072 , G06F12/1036 , G06F12/126
Abstract: Systems, methods and apparatuses to throttle network communications for memory as a service are described. For example, a computing device can borrow an amount of random access memory of the lender device over a communication connection between the lender device and the computing device. The computing device can allocate virtual memory to applications running in the computing device, and configure at least a portion of the virtual memory to be hosted on the amount of memory loaned by the lender device to the computing device. The computing device can throttle data communications used by memory regions in accessing the amount of memory over the communication connection according to the criticality levels of the contents stored in the memory regions.
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公开(公告)号:US11256624B2
公开(公告)日:2022-02-22
申请号:US16424421
申请日:2019-05-28
Applicant: Micron Technology, inc.
Inventor: Kenneth Marion Curewitz , Ameen D. Akel , Samuel E. Bradshaw , Sean Stephen Eilert , Dmitri Yudanov
IPC: G06F12/00 , G06F12/0837 , G06F12/1027 , G06F11/14 , G06F9/38 , G06F12/1009 , G06F13/00 , G06F13/28 , G06N3/02
Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.
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