公开(公告)号：US07576668B2

公开(公告)日：2009-08-18

申请号：US11934611

申请日：2007-11-02

Applicant: Anand Hariraj Udupa ,  Vikas Kumar Sinha ,  Nitin Agarwal ,  Visvesvararaya A. Pentakota ,  Sandeep Oswal

Inventor： Anand Hariraj Udupa ,  Vikas Kumar Sinha ,  Nitin Agarwal ,  Visvesvararaya A. Pentakota ,  Sandeep Oswal

IPC: H03M1/00

CPC classification number: H03M1/168

Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

Abstract translation: 流水线ADC的一个阶段，其使用单独的采样网络和放大器对（在采样和保持电路（SHA）中）来向量化器（其产生子代码）和开关电容器网络（实现DAC， 减法器和放大）。 由于使用单独的组件/路径来提供输入信号，因此增强了ADC的吞吐量性能。

公开(公告)号：US07479915B1

公开(公告)日：2009-01-20

申请号：US11959494

申请日：2007-12-19

Applicant: Ramesh Kumar Singh ,  Nitin Agarwal ,  Abhaya Kumar ,  Visvesvarya Pentakota A

Inventor： Ramesh Kumar Singh ,  Nitin Agarwal ,  Abhaya Kumar ,  Visvesvarya Pentakota A

IPC: H03M1/38

CPC classification number: H03K5/2481 ,  H03M1/167

Abstract: A comparator presents a linear load to input signals when providing a comparison output of two input signals. The comparator contains a transistor configured in a source/emitter follower configuration, and operates in the saturation region for substantially the entire range of strengths of the input signals. As a result, the comparator presents a substantially constant load to the input signals. When incorporated in circuits such as a pipeline ADC, the comparator may substantially eliminate errors due to non-linear loads.

Abstract translation: 当提供两个输入信号的比较输出时，比较器向输入信号提供线性负载。 比较器包含配置在源/射极跟随器配置中的晶体管，并且在输入信号的基本上整个强度范围内在饱和区域中工作。 结果，比较器对输入信号施加基本恒定的负载。 当结合到诸如流水线ADC的电路中时，比较器可以基本上消除由于非线性负载引起的误差。

公开(公告)号：US20080055129A1

公开(公告)日：2008-03-06

申请号：US11934611

申请日：2007-11-02

Applicant: Anand Udupa ,  Vikas Sinha ,  Nitin Agarwal ,  Visvesvararaya Pentakota ,  Sandeep Oswal

Inventor： Anand Udupa ,  Vikas Sinha ,  Nitin Agarwal ,  Visvesvararaya Pentakota ,  Sandeep Oswal

IPC: H03M1/12

CPC classification number: H03M1/168

Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

Abstract translation: 流水线ADC的一个阶段，其使用单独的采样网络和放大器对（在采样和保持电路（SHA）中）来向量化器（其产生子代码）和开关电容器网络（实现DAC， 减法器和放大）。 由于使用单独的组件/路径来提供输入信号，因此增强了ADC的吞吐量性能。

公开(公告)号：US20070229175A1

公开(公告)日：2007-10-04

申请号：US11638306

申请日：2006-12-12

Applicant: Nitin Agarwal ,  Kallol Chatterjee

Inventor： Nitin Agarwal ,  Kallol Chatterjee

IPC: H03L7/00

CPC classification number: H03L7/0891 ,  H03L7/093

Abstract: The invention relates to an improved phase locked loop (PLL) circuit for preventing erroneous condition in the charge pump operation. The invention includes modification in the PLL circuitry by adding delay elements for connection between the phase frequency detector and the charge pump and a digital logic circuit for obtaining the clock signals for the loop filter.

Abstract translation: 本发明涉及一种用于防止电荷泵操作中的错误状态的改进的锁相环（PLL）电路。 本发明包括通过添加用于相位频率检测器和电荷泵之间的连接的延迟元件和用于获得环路滤波器的时钟信号的数字逻辑电路来修改PLL电路。

公开(公告)号：US06995592B2

公开(公告)日：2006-02-07

申请号：US10704210

申请日：2003-11-06

Applicant: Nitin Agarwal

Inventor： Nitin Agarwal

IPC: H03K3/017

CPC classification number: G06F1/08

Abstract: A method and system for generating variable frequency cyclic waveforms using pulse width modulation (PWM) to provide adjustable precision frequency and enhanced resolution is disclosed. The technique includes a plurality of sets of duty cycle values, each set corresponding to the desired waveform profile at a given frequency, coupled with a mechanism for applying a selected duty cycle for a variable number of PWM cycles, to achieve an adjustable fine resolution of the waveform frequency.

Abstract translation: 公开了一种使用脉宽调制（PWM）产生可变频率循环波形以提供可调精度频率和增强分辨率的方法和系统。 该技术包括多个工作周期值集合，每个集合对应于给定频率处的期望波形分布，以及用于对可变数量的PWM周期施加所选择的占空比的机制，以实现可调节的精细分辨率 波形频率。