公开(公告)号：US20080191352A1

公开(公告)日：2008-08-14

申请号：US11706553

申请日：2007-02-13

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的金属化层; 在所述半导体衬底和所述金属化层之间的第一介电层; 在所述半导体衬底和所述金属化层之间的第二电介质层，其中所述第二电介质层在所述第一介电层上; 以及具有基本上在第二电介质层中的上部的接触插塞和基本上在第一电介质层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处是不连续的。

公开(公告)号：US20060108696A1

公开(公告)日：2006-05-25

申请号：US11328614

申请日：2006-01-10

申请人： Chih-Hsiang Yao ,  Chin-Chiu Hsia ,  Wen-Kai Wan

发明人： Chih-Hsiang Yao ,  Chin-Chiu Hsia ,  Wen-Kai Wan

IPC分类号： H01L23/48

CPC分类号： H01L23/528 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.

摘要翻译： 一种用于减小集成电路的互连中的应力引起的空隙的结构，所述互连具有第一部分和至少第二部分比第一部分更窄的部分。 该结构包括设置在第一部分中的靠近第一部分和第二部分的相交处的至少一个内部狭槽。 本发明还包括制造互连和结构的方法。 导电互连结构包括第一部分和比第一部分更窄的至少第二部分; 以及包括形成在所述第一部分和所述第二部分的交叉点处的过渡部分的应力减小结构。

公开(公告)号：US06812069B2

公开(公告)日：2004-11-02

申请号：US10322691

申请日：2002-12-17

申请人： Tung-Ching Tseng ,  Syun-Ming Jang ,  Chih-Hsiang Yao

发明人： Tung-Ching Tseng ,  Syun-Ming Jang ,  Chih-Hsiang Yao

IPC分类号： H01L2182

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for improving CMP polishing uniformity and reducing or preventing cracking in a semiconductor wafer process surface by reducing stress concentrations adjacent to dummy features including providing a semiconductor wafer process surface including active features and dummy features formed adjacently to the active features to improve a CMP polishing uniformity said dummy features each shaped to define an enclosed area in said semiconductor wafer process surface plane comprising at least 5 corner portions; and, performing a CMP process on said semiconductor wafer process surface.

摘要翻译： 一种通过减少与虚拟特征相邻的应力集中来提高CMP抛光均匀性并减少或防止半导体晶片工艺表面中的裂纹的方法，包括提供半导体晶片工艺表面，其包括与活性特征相邻形成的活性特征和虚拟特征，以改善CMP抛光 均匀性，所述虚拟特征各自被成形为在包括至少5个角部的所述半导体晶片工艺表面中限定封闭区域; 以及在所述半导体晶片处理表面上执行CMP处理。

公开(公告)号：US06759342B2

公开(公告)日：2004-07-06

申请号：US10269219

申请日：2002-10-11

申请人： Chih-Hsiang Yao ,  Lain-Jong Li ,  Bi-Troug Chen ,  Syun-Ming Jan

发明人： Chih-Hsiang Yao ,  Lain-Jong Li ,  Bi-Troug Chen ,  Syun-Ming Jan

IPC分类号： H01L21302

CPC分类号： H01L21/3105 ,  H01J2237/0206 ,  H01J2237/3342 ,  H01L21/31116

摘要： A method for reducing electrical charge imbalances in a semiconductor process wafer including providing a semiconductor process wafer including a dielectric insulating layer; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates in charge imbalance portions of the dielectric insulating layer; and, treating the semiconductor process wafer with a controlled atmosphere of treatment gas including at least one of inert gas and hydrogen to reduce an accumulated charge imbalance in the charge imbalance portions.

摘要翻译： 一种用于减少半导体工艺晶片中的电荷不平衡的方法，包括提供包括介电绝缘层的半导体工艺晶片; 将半导体工艺晶片暴露于半导体工艺，由此电荷不平衡累积在电介质绝缘层的电荷不平衡部分中; 以及在包含惰性气体和氢气中的至少一种的处理气体的受控气氛下处理所述半导体处理晶片以减少所述电荷不平衡部分中的累积电荷不平衡。

公开(公告)号：US08692351B2

公开(公告)日：2014-04-08

申请号：US12753272

申请日：2010-04-02

申请人： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

发明人： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

IPC分类号： H01L21/70

CPC分类号： H01L21/76838 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

摘要翻译： 在本公开中描述了用于改善密集到隔离图案转移区域附近的处理窗口的半导体集成电路线结构和在布局处理中实现线结构的技术。 所公开的结构包括半导体衬底和衬底上方的材料层。 材料层具有紧密间隔的密集线结构，紧密密集线结构旁边的隔离线结构，以及形成在密集线附近和隔离线结构处的虚拟线肩结构。 虚拟线肩结构的一端连接到隔离线结构，另一端以基本垂直于隔离线结构的方向远离隔离线结构延伸。

公开(公告)号：US20130207273A1

公开(公告)日：2013-08-15

申请号：US13370919

申请日：2012-02-10

申请人： Chih-Hsiang Yao ,  Ying-Wen Huang

发明人： Chih-Hsiang Yao ,  Ying-Wen Huang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/522 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76816 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a dielectric layer, a metal line in the dielectric layer, and a via underlying and connected to the metal line. Two dummy metal patterns are adjacent to the metal line, and are aligned to a straight line. A dummy metal line interconnects the two dummy metal patterns. A width of the dummy metal line is smaller than lengths and widths of the two dummy metal patterns, wherein the width is measure in a direction perpendicular to the straight line. Bottoms of the two dummy metal patterns and the dummy metal line are substantially level with a bottom surface of the metal line.

摘要翻译： 一种器件包括电介质层，电介质层中的金属线以及下面并连接到金属线的通孔。 两个虚拟金属图案与金属线相邻，并且与直线对准。 虚拟金属线将两个虚拟金属图案互连。 虚拟金属线的宽度小于两个虚拟金属图案的长度和宽度，其中宽度在垂直于直线的方向上测量。 两个虚拟金属图案和虚拟金属线的底部基本上与金属线的底面平齐。

公开(公告)号：US20110092019A1

公开(公告)日：2011-04-21

申请号：US12973707

申请日：2010-12-20

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L21/60

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成金属化层; 在所述半导体衬底和所述金属化层之间形成第一电介质层; 在所述半导体衬底和所述金属化层之间形成第二电介质层，其中所述第二电介质层在所述第一电介质层的上方; 以及形成具有基本上在所述第二介电层中的上部的接触塞和基本在所述第一介电层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处是不连续的。

公开(公告)号：US07042097B2

公开(公告)日：2006-05-09

申请号：US10455849

申请日：2003-06-06

申请人： Chih-Hsiang Yao ,  Chin-Chiu Hsia ,  Wen-Kai Wan

发明人： Chih-Hsiang Yao ,  Chin-Chiu Hsia ,  Wen-Kai Wan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/528 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.