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    Dummy shoulder structure for line stress reduction
    1.
    发明授权
    Dummy shoulder structure for line stress reduction 有权
    用于线应力降低的假肩结构

    公开(公告)号：US08692351B2

    公开(公告)日：2014-04-08

    申请号：US12753272

    申请日：2010-04-02

    申请人： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

    发明人： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76838 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

    摘要翻译： 在本公开中描述了用于改善密集到隔离图案转移区域附近的处理窗口的半导体集成电路线结构和在布局处理中实现线结构的技术。 所公开的结构包括半导体衬底和衬底上方的材料层。 材料层具有紧密间隔的密集线结构，紧密密集线结构旁边的隔离线结构，以及形成在密集线附近和隔离线结构处的虚拟线肩结构。 虚拟线肩结构的一端连接到隔离线结构，另一端以基本垂直于隔离线结构的方向远离隔离线结构延伸。

    DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION
    2.
    发明申请
    DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION 有权
    用于线应力减少的双层结构

    公开(公告)号：US20110241207A1

    公开(公告)日：2011-10-06

    申请号：US12753272

    申请日：2010-04-02

    申请人： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

    发明人： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

    IPC分类号： H01L23/52 ,  G06F17/50

    CPC分类号： H01L21/76838 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

    摘要翻译： 在本公开中描述了用于改善密集到隔离图案转移区域附近的处理窗口的半导体集成电路线结构和在布局处理中实现线结构的技术。 所公开的结构包括半导体衬底和衬底上方的材料层。 材料层具有紧密间隔的密集线结构，紧密密集线结构旁边的隔离线结构，以及形成在密集线附近和隔离线结构处的虚拟线肩结构。 虚拟线肩结构的一端连接到隔离线结构，另一端以基本垂直于隔离线结构的方向远离隔离线结构延伸。

    SUB-RESOLUTION ASSIST FEATURE OF A PHOTOMASK
    4.
    发明申请
    SUB-RESOLUTION ASSIST FEATURE OF A PHOTOMASK 审中-公开
    照片的分辨率辅助功能

    公开(公告)号：US20090258302A1

    公开(公告)日：2009-10-15

    申请号：US12100907

    申请日：2008-04-10

    申请人： Jeng-Shiun Ho ,  Jun-Hua Chen ,  Luke Lo ,  Louis Lin ,  Bing-Syun Yeh ,  Cheng-Cheng Kuo ,  Hua-Tai Lin

    发明人： Jeng-Shiun Ho ,  Jun-Hua Chen ,  Luke Lo ,  Louis Lin ,  Bing-Syun Yeh ,  Cheng-Cheng Kuo ,  Hua-Tai Lin

    IPC分类号： G03F1/00 ,  G06F17/50

    CPC分类号： G03F1/36

    摘要： A photomask including a main feature, corresponding to an integrated circuit feature, and a sub-resolution assist feature (SRAF) is provided. A first imaginary line tangential with a first edge of the main feature and a second imaginary line tangential with the second edge of the main feature define an area adjacent the main feature. A center point of the SRAF lies within this area. The SRAF may be a symmetrical feature. In an embodiment, the center point of the SRAF lies on an imaginary line extending at approximately 45-degree angle from a corner of a main feature.

    摘要翻译： 提供了包括对应于集成电路特征的主要特征的光掩模和子分辨率辅助特征（SRAF）。 与主要特征的第一边缘切线的第一虚拟线和与主要特征的第二边缘相切的第二假想线切线限定与主要特征相邻的区域。 SRAF的中心位于该区域内。 SRAF可以是对称的特征。 在一个实施例中，SRAF的中心点位于从主要特征的角度以大约45度角延伸的假想线上。

    OPTICAL PROXIMITY CORRECTION CONVERGENCE CONTROL
    6.
    发明申请
    OPTICAL PROXIMITY CORRECTION CONVERGENCE CONTROL 有权
    光临近度校正综合控制

    公开(公告)号：US20130205265A1

    公开(公告)日：2013-08-08

    申请号：US13368919

    申请日：2012-02-08

    申请人： Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Tzu-Chun Lo ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Tsai-Sheng Gau ,  Wen-Chun Huang ,  Chih-Shiang Chou ,  Hsin-Chang Lee ,  Kuei Shun Chen

    发明人： Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Tzu-Chun Lo ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Tsai-Sheng Gau ,  Wen-Chun Huang ,  Chih-Shiang Chou ,  Hsin-Chang Lee ,  Kuei Shun Chen

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70441 ,  G03F7/70125

    摘要： A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.

    摘要翻译： 一种光学邻近校正（OPC）会聚控制的方法，包括提供具有光掩模和照明器的光刻系统。 该方法还包括执行照明器在光掩模上的曝光。 此外，该方法包括在第一模板中以第一方向限定的门间距优化光刻系统的光照射器设置。 此外，该方法包括确定OPC校正器以使目标边缘放置误差（EPE）收敛OPC结果，以产生第一模板的第一OPC设置。 第一个OPC设置针对第一个模板中定义的门间距的相对较小的EPE和掩模误差增强因子（MEEF）。 此外，该方法包括在第二相邻模板中检查与相对小的EPE，MEEF和DOM一致性的第一OPC设置与限定的门间距的第一模板。

    Optical proximity correction convergence control
    7.
    发明授权
    Optical proximity correction convergence control 有权
    光学接近校正收敛控制

    公开(公告)号：US08656319B2

    公开(公告)日：2014-02-18

    申请号：US13368919

    申请日：2012-02-08

    申请人： Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Tzu-Chun Lo ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Tsai-Sheng Gau ,  Wen-Chun Huang ,  Chih-Shiang Chou ,  Hsin-Chang Lee ,  Kuei Shun Chen

    发明人： Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Tzu-Chun Lo ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Tsai-Sheng Gau ,  Wen-Chun Huang ,  Chih-Shiang Chou ,  Hsin-Chang Lee ,  Kuei Shun Chen

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70441 ,  G03F7/70125

    摘要： A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.

    摘要翻译： 一种光学邻近校正（OPC）会聚控制的方法，包括提供具有光掩模和照明器的光刻系统。 该方法还包括执行照明器在光掩模上的曝光。 此外，该方法包括在第一模板中以第一方向限定的门间距优化光刻系统的光照射器设置。 此外，该方法包括确定OPC校正器以使目标边缘放置误差（EPE）收敛OPC结果，以产生第一模板的第一OPC设置。 第一个OPC设置针对第一个模板中定义的门间距的相对较小的EPE和掩模误差增强因子（MEEF）。 此外，该方法包括在第二相邻模板中检查第一OPC设置以获得相对较小的EPE，MEEF和DOM与限定的门间距的第一模板的一致性。

    Method and apparatus for reducing spin-induced wafer charging
    9.
    发明申请
    Method and apparatus for reducing spin-induced wafer charging 审中-公开
    减少自旋晶片充电的方法和装置

    公开(公告)号：US20060000109A1

    公开(公告)日：2006-01-05

    申请号：US10884714

    申请日：2004-07-03

    申请人： Hua-Tai Lin ,  Shih-Che Wang ,  Louie Liu ,  Chi-Hung Liao ,  Yi-Ming Dai

    发明人： Hua-Tai Lin ,  Shih-Che Wang ,  Louie Liu ,  Chi-Hung Liao ,  Yi-Ming Dai

    IPC分类号： C23G1/02 ,  F26B5/08 ,  F26B17/24

    CPC分类号： H01L21/67051 ,  B08B3/10 ,  H01L21/67028 ,  H01L21/67034

    摘要： A novel method and apparatus for reducing or eliminating electrostatic charging of wafers during a spin-dry step of wafer cleaning is disclosed. The method includes rinsing a wafer, typically by dispensing a cleaning liquid such as deionized water on the wafer while spinning the wafer; and spin-drying the wafer by sequentially rotating the wafer in opposite directions. The apparatus includes a wafer support platform that is capable of sequentially rotating a wafer in opposite directions to spin-dry the wafer.

    摘要翻译： 公开了一种在晶片清洗的旋转干燥步骤中减少或消除晶片的静电充电的新型方法和装置。 该方法包括冲洗晶片，通常通过在旋转晶片的同时在晶片上分配诸如去离子水的清洁液体; 并通过沿相反方向顺序旋转晶片来旋转晶片。 该装置包括能够沿相反方向顺序旋转晶片以旋转晶片的晶片支撑平台。