公开(公告)号：US20080191352A1

公开(公告)日：2008-08-14

申请号：US11706553

申请日：2007-02-13

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的金属化层; 在所述半导体衬底和所述金属化层之间的第一介电层; 在所述半导体衬底和所述金属化层之间的第二电介质层，其中所述第二电介质层在所述第一介电层上; 以及具有基本上在第二电介质层中的上部的接触插塞和基本上在第一电介质层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处是不连续的。

公开(公告)号：US08450200B2

公开(公告)日：2013-05-28

申请号：US12973707

申请日：2010-12-20

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成金属化层; 在所述半导体衬底和所述金属化层之间形成第一电介质层; 在所述半导体衬底和所述金属化层之间形成第二电介质层，其中所述第二电介质层在所述第一电介质层的上方; 以及形成具有基本上在所述第二介电层中的上部的接触塞和基本在所述第一介电层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处不连续。

公开(公告)号：US07880303B2

公开(公告)日：2011-02-01

申请号：US11706553

申请日：2007-02-13

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的金属化层; 在所述半导体衬底和所述金属化层之间的第一介电层; 在所述半导体衬底和所述金属化层之间的第二电介质层，其中所述第二电介质层在所述第一介电层上; 以及具有基本上在第二电介质层中的上部的接触插塞和基本上在第一电介质层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处是不连续的。

公开(公告)号：US20110092019A1

公开(公告)日：2011-04-21

申请号：US12973707

申请日：2010-12-20

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L21/60

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成金属化层; 在所述半导体衬底和所述金属化层之间形成第一电介质层; 在所述半导体衬底和所述金属化层之间形成第二电介质层，其中所述第二电介质层在所述第一电介质层的上方; 以及形成具有基本上在所述第二介电层中的上部的接触塞和基本在所述第一介电层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处是不连续的。

公开(公告)号：US11038056B2

公开(公告)日：2021-06-15

申请号：US13371169

申请日：2012-02-10

申请人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20

摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

公开(公告)号：US08110890B2

公开(公告)日：2012-02-07

申请号：US11758043

申请日：2007-06-05

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Ding-Yuan Chen

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Ding-Yuan Chen

IPC分类号： H01L21/70

CPC分类号： H01L21/76202 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.

摘要翻译： 包括可折入隔离结构的半导体器件和用于制造这种器件的方法。 优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。 至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。 在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。

公开(公告)号：US20120025313A1

公开(公告)日：2012-02-02

申请号：US13272994

申请日：2011-10-13

申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L27/12 ,  H01L29/02

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以在硅片上形成包括硅翅片和冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US08048723B2

公开(公告)日：2011-11-01

申请号：US12329279

申请日：2008-12-05

申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L21/332

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以形成包括硅片和在硅微细上的冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US20110037129A1

公开(公告)日：2011-02-17

申请号：US12912522

申请日：2010-10-26

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L29/78

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.

摘要翻译： 提供具有多个翅片高度的半导体器件。 通过使用多个掩模来在形成在衬底中的沟槽内凹入电介质层来提供多个翅片高度。 在另一个实施例中，使用植入模具或电子束光刻来形成光致抗蚀剂材料中的沟槽图案。 随后的蚀刻步骤在下面的衬底中形成对应的沟槽。 在另一个实施例中，使用多个掩模层来分别蚀刻不同高度的沟槽。 可以沿着沟槽的底部形成电介质区域，以通过执行离子注入和随后的退火来隔离散热片。

公开(公告)号：US20090278196A1

公开(公告)日：2009-11-12

申请号：US12116074

申请日：2008-05-06

申请人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh

发明人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L29/1083 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/7843 ,  H01L29/7851

摘要： A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

摘要翻译： 半导体结构包括半导体衬底; 在所述半导体衬底的第一部分上的平面晶体管，其中所述半导体衬底的所述第一部分具有第一顶表面; 以及在半导体衬底的第二部分上的多栅极晶体管。 半导体衬底的第二部分从第一顶表面凹入以形成多栅晶体管的鳍。 翅片通过绝缘体与半导体衬底电隔离。